Patents by Inventor John A. Olenick

John A. Olenick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190165342
    Abstract: A thin-film battery that includes an adhesive layer is provided. The thin-film battery may have active layer (such as an anode, a cathode, an electrolyte, an anode current collector, and a cathode current collector) and a thin-film substrate made of ceramic or glass. The adhesive layer may be deposited over a portion of the active layer and the substrate. This may provide for a more stable, flexible, and mechanically sound thin-film battery.
    Type: Application
    Filed: July 13, 2017
    Publication date: May 30, 2019
    Applicant: ITN Energy Systems, Inc.
    Inventors: Brian BERLAND, John OLENICK, Kathy OLENICK, David CAREY
  • Publication number: 20180122969
    Abstract: Kesterite-based photovoltaic devices formed on flexible ceramic substrates are provided. In one aspect, a method of forming a photovoltaic device includes the steps of: forming a back contact on a flexible ceramic substrate; forming a kesterite absorber layer on a side of the back contact opposite the flexible ceramic substrate; annealing the kesterite absorber layer; forming a buffer layer on a side of the kesterite absorber layer opposite the back contact; and forming a transparent front contact on a side of the buffer layer opposite the kesterite absorber layer. A roll-to-roll-based method of forming a photovoltaic device and a photovoltaic device are also provided.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 3, 2018
    Inventors: John A. Olenick, Teodor K. Todorov
  • Patent number: 9917216
    Abstract: Kesterite-based photovoltaic devices formed on flexible ceramic substrates are provided. In one aspect, a method of forming a photovoltaic device includes the steps of: forming a back contact on a flexible ceramic substrate; forming a kesterite absorber layer on a side of the back contact opposite the flexible ceramic substrate; annealing the kesterite absorber layer; forming a buffer layer on a side of the kesterite absorber layer opposite the back contact; and forming a transparent front contact on a side of the buffer layer opposite the kesterite absorber layer. A roll-to-roll-based method of forming a photovoltaic device and a photovoltaic device are also provided.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: John A. Olenick, Teodor K. Todorov
  • Publication number: 20160126377
    Abstract: Kesterite-based photovoltaic devices formed on flexible ceramic substrates are provided. In one aspect, a method of forming a photovoltaic device includes the steps of: forming a back contact on a flexible ceramic substrate; forming a kesterite absorber layer on a side of the back contact opposite the flexible ceramic substrate; annealing the kesterite absorber layer; forming a buffer layer on a side of the kesterite absorber layer opposite the back contact; and forming a transparent front contact on a side of the buffer layer opposite the kesterite absorber layer. A roll-to-roll-based method of forming a photovoltaic device and a photovoltaic device are also provided.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 5, 2016
    Inventors: John A. Olenick, Teodor K. Todorov
  • Patent number: 7281412
    Abstract: A high-temperature seal having in-situ integrity monitoring capability includes a quantity of dielectric material sealing an interface between adjacent structures and an electrical transmission line embedded within the dielectric material. A signal injection port is provided for exciting the transmission line with an excitation signal. One or more sample ports are provided for sampling the transmission line to obtain signal samples resulting from the excitation signal. The sample port(s) are adapted for connection to a signal analyzer adapted to analyze the signal samples for indications of seal integrity problems. Using a technique such as time domain reflectometry or frequency response analysis, the transmission line can be monitored for changes in characteristic impedance due to changes in seal dielectric constant and/or disruption of the transmission line.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: October 16, 2007
    Inventors: John A. Olenick, Timothy J. Curry, Robert A. Bourdelaise, Eli A. Richards, Paul A. Vichot, Barry E. Grabow, Samuel F. Wilderson
  • Publication number: 20070051193
    Abstract: A high-temperature seal having in-situ integrity monitoring capability includes a quantity of dielectric material sealing an interface between adjacent structures and an electrical transmission line embedded within the dielectric material. A signal injection port is provided for exciting the transmission line with an excitation signal. One or more sample ports are provided for sampling the transmission line to obtain signal samples resulting from the excitation signal. The sample port(s) are adapted for connection to a signal analyzer adapted to analyze the signal samples for indications of seal integrity problems. Using a technique such as time domain reflectometry or frequency response analysis, the transmission line can be monitored for changes in characteristic impedance due to changes in seal dielectric constant and/or disruption of the transmission line.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 8, 2007
    Inventors: John Olenick, Timothy Curry, Robert Bourdelaise, Eli Richards, Paul Vichot, Barry Grabow, Samuel Wilderson
  • Patent number: 6501643
    Abstract: A carrying case (either a soft case or a hard case) is taught that includes a section or compartment for receiving a personal digital assistant device that allows for access to the controls in view of the display without removing the device from the carrying case when the case is opened. Additionally, the carrying case is provided with a second compartment independent of the section or compartment for receiving the personal digital assistant device. The second compartment is adapted to receive an ancillary device such that when a user desires to use the ancillary device, the user removes the ancillary device from its compartment and also removes the personal digital assistant from its compartment and interconnects the two to allow for operation of the ancillary device. However, when the user desires to use the personal digital assistant alone, it is only necessary to open the carrying case and operate the personal digital assistant without having to remove it from the carrying case.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: December 31, 2002
    Assignee: Eastman Kodak Company
    Inventors: Barbara A. Sayers, John A. Olenick
  • Patent number: 5440805
    Abstract: In accordance with the present invention, a circuit assembly is manufactured in an additive process using at least one layer of a fluoropolymer composite material and a conductive material. The conductive layers are plated, and the fluoropolymer composite layers are laminated. The use of the filled fluoropolymeric composite eliminates the need for a barrier metal layer between the insulation and the conductors. A plurality of these circuit assemblies are stacked, one on top of the other. At least, selected exposed locations of the conductive material comprise a diffusible conductive material (e.g., gold). Once stacked the circuit assemblies are subjected to lamination under heat and pressure to simultaneously fuse adjacent fluoropolymer composite material and diffuse adjacent diffusible conductive material together to form an integral multilayer circuit having solid conductive interconnects.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: August 15, 1995
    Assignee: Rogers Corporation
    Inventors: Robert C. Daigle, W. David Smith, John A. Olenick, David J. Arthur, Gwo S. Swei
  • Patent number: 5329695
    Abstract: Methods of fabricating multilayer circuits are presented. In accordance with the present invention, a plurality of circuit layers are stacked, one on top of the other. At least one of the circuit layers comprise a substrate composed of a polymeric material capable of undergoing bonding such as a fluoropolymeric based substrate having vias therethrough and a circuit comprised of a layer of suitable conductive material. A fusible conductive bonding material (e.g., solder) or a noble metal is applied wherever electrical connections are desired. At least one other of the circuit layers comprises a cofired multilayer ceramic circuit having vias and circuits comprised of a layer of suitable conductive material with a fusible conductive bonding material (e.g., solder) or a noble metal applied wherever electrical connections are desired.
    Type: Grant
    Filed: December 31, 1992
    Date of Patent: July 19, 1994
    Assignee: Rogers Corporation
    Inventors: Richard T. Traskos, John A. Olenick
  • Patent number: 5287619
    Abstract: In accordance with the present invention, an MCM substrate product is manufactured in an additive process using multiple layers of a fluoropolymer composite material and copper. The copper layers are plated, and the fluoropolymer composite layers are laminated. A seeding process promotes reliable bonding between the fluoropolymer composite material and the plated copper. The use of the filled fluoropolymeric composite eliminates the need for a barrier metal layer between the insulation and the conductors. The MCM substrate device of the present invention may have multiple metal layers and multiple dielectric layers; four or five, or more, of each in a single structure would be easily achieved and is typical. The structure would include lead lines in separate mutually orthogonal planes (sometimes referred to as "x" and "y" lead lines) sandwiched between ground and power voltage planes of copper.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: February 22, 1994
    Assignee: Rogers Corporation
    Inventors: W. David Smith, John A. Olenick, Carlos L. Barton, Jane L. Cercena, Daniel J. Navarro, Kathleen R. Olenick, Angela M. Kneeland, Thomas S. Kneeland, Mark F. Sylvester, Curtis H. Kempton, Scott E. Derosier, Lynn E. Burdick, Richard T. Traskos, Robert B. Huntington, James S. Rivers, Samuel Gazit, Jeffrey B. Ott, William P. Harper
  • Patent number: 5274912
    Abstract: Methods of fabricating multilayer circuits are presented. In accordance with the present invention, a plurality of circuit layers comprised of a dielectric substrate having a circuit formed thereon are stacked, one on top of the other. The dielectric substrate is composed of a polymeric material capable of undergoing fusion bonding such as a fluoropolymeric based substrate. The circuits each include a layer of a noble metal at, at least, selected exposed locations. Once stacked the circuits are subjected to lamination under heat and pressure to simultaneously fuse all of the substrate and diffuse conductive layers together to form an integral multilayer circuit having solid conductive interconnects.
    Type: Grant
    Filed: September 1, 1992
    Date of Patent: January 4, 1994
    Assignee: Rogers Corporation
    Inventors: John A. Olenick, Robert C. Daigle
  • Patent number: 5041695
    Abstract: Both a co-fired ceramic package for a power circuit is disclosed as well as a method of manufacture thereof. The package includes a base which is formed from a plurality of pyrolizable ceramic films, each of which includes a heat-conductive and electrically insulative ceramic material such as aluminum nitride, silicon carbide or beryllium oxide embedded within a binder. In the method of the invention, two or three ceramic films are metalized with a pattern of conductive material on their top surfaces. The resulting metalized films are then stacked over a plurality of unmetalized ceramic films, and the resulting aggregate stack is laminated together by the application of heat and pressure. Electrical components are then soldered onto the top surface of the base, and a cover is sealingly connected around the resulting hybrid circuit. The metalization step advantageously forms terminals around the cover which allow access to the heat generating power circuit without the need for glass post seals.
    Type: Grant
    Filed: June 1, 1989
    Date of Patent: August 20, 1991
    Assignee: Westinghouse Electric Corp.
    Inventors: John A. Olenick, Allen B. Timberlake
  • Patent number: 5027191
    Abstract: The invention is an improved chip carrier assembly utilizing a cavity-down chip carrier with a pad grid array wherein the IC chip within the chip carrier is mounted against a surface opposite the PWB to which the chip carrier is attached such that heat transfer from the IC chip may occur along a short path to a heat sink such that a large heat transfer rate is possible. Furthermore, the apparatus utilizes an alignment and electrical connection means between the contact pads of the chip carrier and a PWB to which the chip carrier is attached to compensate for shrinkage variation which occurs during the chip carrier fabrication process. Furthermore, within the cavity of the chip carrier there is space for additional components such as a decoupling capacitors. This permits the design of an apparatus providing better heat transfer properties, more accurate contact pad locations and the option of including within the chip carrier components which in the past had been mounted outside of the chip carrier.
    Type: Grant
    Filed: May 11, 1989
    Date of Patent: June 25, 1991
    Assignee: Westinghouse Electric Corp.
    Inventors: Robert A. Bourdelaise, David B. Harris, Denise B. Harris, John A. Olenick