Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: A system for depositing a layer on a substrate includes a processing chamber including a gas inlet, a plurality of gas flow controllers connected in fluid communication with a gas supply source, a gas distribution plate disposed between the plurality of gas flow controllers and the gas inlet, and a gas injection cap connected in fluid communication between the plurality of gas flow controllers and the gas distribution plate. The gas distribution plate defines a plurality of holes, and the gas injection cap defines a plurality of gas flow passages, each extending from an inlet connected to one of the gas flow controllers to an outlet connected in fluid communication with at least one of the holes in the gas distribution plate. Each of the gas flow controllers is disposed proximate to the gas injection cap.

Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Abstract: A system for depositing a layer on a substrate includes a processing chamber including a gas inlet, a plurality of gas flow controllers connected in fluid communication with a gas supply source, a gas distribution plate disposed between the plurality of gas flow controllers and the gas inlet, and a gas injection cap connected in fluid communication between the plurality of gas flow controllers and the gas distribution plate. The gas distribution plate defines a plurality of holes, and the gas injection cap defines a plurality of gas flow passages, each extending from an inlet connected to one of the gas flow controllers to an outlet connected in fluid communication with at least one of the holes in the gas distribution plate. Each of the gas flow controllers is disposed proximate to the gas injection cap.

Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Abstract: The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.

Abstract: A barrel susceptor for supporting semiconductor wafers in a heated chamber having an interior space. Each of the wafers has a front surface, a back surface and a circumferential side. The susceptor includes a body having a plurality of faces arranged around an imaginary central axis of the body. Each face has an outer surface and a recess extending laterally inward into the body from the outer surface. Each recess is surrounded by a rim defining the respective recess. The susceptor also includes a plurality of ledges extending outward from the body. Each of the ledges is positioned in one of the recesses and includes an upward facing support surface for supporting a semiconductor wafer received in the recess. Each of the support surfaces is separate from the outer surface of the respective face.

Abstract: Systems and computer-readable media having computer-executable components are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.

Abstract: The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.