Abstract: An emergency air system for kayaks is disclosed. The emergency air system can be coupled to a kayak skirt or may be coupled to the body of the kayak. The air system includes a breathing tube which includes a mouthpiece. Preferably, the breathing tube is secured to the kayak skirt or the kayak body with a pair of opposing, flat washers.

Abstract: An apparatus and method are disclosed for switching the arrays of parallel memory data structures upon the detection of defects in a memory storage device. To date, redundancy has been implemented using duplicate arrays connected to laser zappable fuses. The use of laser zappable fuses imposes restrictive technology constraints. In particular, to avoid damage to surrounding circuity when a fuse is "zapped," considerable space must be allowed between each fuse and other fuses or other unrelated circuitry. The present invention uses only two extra parallel arrays to correct for any open or short defects in a parallel memory data structure, and does it with a nearly constant array length as the original arrays. The redundant arrays as well as the original arrays are connected to toggle switches. Upon encountering any open or short in the one or more data paths, the toggle switches coupled to the open or short are "flipped" to connect to the adjacent data paths in a cascading fashion.

Abstract: A downhole tool positioned intermediate the mud motor and the drill bit, for reducing the hydro-static head near or around the bit. What is provided is an upper body portion threadably attachable to the mud motor and having an internal shaft with a bore therethrough for allowing mud to flow down the shaft rotatable during the the operation of the tool. The upper body portion further includes a gear member on the outer wall of the shaft for rotatably engaging the pair of upper gear members which imparts rotation to a pair of lower gear members for further imparting rotation to a fan member located in the lower portion of the tool.

Abstract: A memory array of four-IGFET-transistor cells arranged in rows and columns. The array uses two patterned metal layers and two patterned poly-silicon layers. For each column there is a pair of metal differential bit lines, formed on a first patterned metal layer. For each row there is a pair of split equipotential poly-silicon word lines and a parallel metal word line with connections to the split poly word lines at defined intervals. The parallel metal word line is on a second patterned metal layer distinct from the metal layer used for the bit lines. A grounded poly-silicon plate overlies the capacitive memory nodes of said array. The grounded poly-silicon plate is on a second patterned poly-silicon layer distinct from the poly-silicon layer used for the split word lines. The poly-silicon plate is connected to the circuit ground at defined intervals. Also, the poly-silicon plate provides alpha particle protection to the array and helps decouple the bit lines from the capacitive nodes of the array.

Abstract: There is described a CMOS random access memory having memory access circuitry which substantially eliminates substrate noise caused by capacitive coupling of the bit lines to the substrate, and which allows the memory to have equal length access and cycle times. Access circuitry for each column of cells includes a pair of differential bit lines, at least one bit line equalization transistor, and a CMOS sense amp. The sense amp has two p-channel pull-up transistors, each having its source node connected to a common pull-up node, and two n-channel pull-down transistors, each having its source node connected to a common pull-down node.At the beginning of each memory access cycle the differential bit lines are equalized and the common pull-up and pull-down nodes are equalized. Then, substantially simultaneously, the common pull-up node is charged while the common pull-down node is discharged.

Abstract: A semiconductor memory is comprised of a semiconductor substrate having first and second spaced apart arrays of memory cells disposed thereon. A plurality of first pairs of bit lines couple to the cells of the first array, and a corresponding plurality of second pairs of bit lines couple to the cells of the second array. Disposed between each first pair and corresponding second pair of bit lines is one X sense amplifier. This amplifier includes a set node selectively coupled to one bit line of the first pair and to one bit line of the second pair, and a reset node selectively coupled to the opposite bit lines of the first and second pair for selectively sensing charge on the four bit lines.

Abstract: In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifier is coupled between the first and second bit portion for sensing the voltage difference therebetween and for latching into one of the two states in response to sensing either a "0" or a "1" accessed to one of the bit line portions from an addressed memory cell to be read out of the memory. A high input impedance amplifier is provided between the respective bit line portion and the respective input terminal of the sensing amplifier for isolating (buffering) the stray capacitance of the sensing amplifier circuit from the capacitance of its bit line. Switchable restore circuitry bypasses each of the isolating line amplifiers for the purposes of restoring electrical potentials read out of the addressed memory cells.

Abstract: In an MOS dynamic random access memory, address input signals are received by individual comparator buffers which generate corresponding individual pairs of complementary address signals in response to respective ones of the input address signals. The pairs of complementary address signals are strobed from the buffers. Each pair of complementary address signals, as strobed from the individual buffers, diverge from a common potential to a pair of stable complementary address signals which are fed to an array of decoder circuits. Each decoder circuit includes an output line which is precharged to a predetermined potential and is selectively discharged in response to the decoded address signals via a plurality of parallel connected decoder transistors. Each decoder transistor includes a gate control electrode for controlling the conduction between first and second other terminals of the respective transistors. The first terminals are connected to the decoder output line.

Abstract: An MOS dynamic buffer circuit described in terms of an inverter and used for inverting a timing signal is disclosed. Through the use of bootstrapping, the output from the inverter is equal to the voltage used to drive the inverter without having conduction through the output transistor when the inverter is not supplying an output signal. Thus, the inverter does not require the large amounts of standby power associated with prior art circuits.