Abstract: In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.

Abstract: In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.

Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs.

Abstract: An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.

Abstract: In accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of memory blocks, and a plurality of continuation routing paths associated with the memory blocks. A plurality of continuation multiplexers, coupled to the continuation routing paths, are adapted to route signals between the memory blocks, between the logic blocks, and/or between the memory blocks and the logic blocks.

Abstract: A programmable logic device (PLD) having a programmable routing structure that employs non-static memory cells, such as dynamic random access memory (DRAM) cells, to control configurable circuit elements, such as pass-transistors and/or MUXes. In a representative embodiment, each DRAM cell is connected to its corresponding configurable circuit element using a buffer adapted to stabilize the output voltage generated by the cell and offset the effect of charge leakage from the cell capacitor. In addition, refresh circuitry associated with the DRAM cell periodically restores the charge in the cell capacitor using a refresh operation that is performed in the background, without disturbing the user functions of the PLD. Advantageously, a relatively large capacitance associated with a DRAM cell makes a PLD of the invention less susceptible to soft errors than a prior-art PLD that relies on SRAM cells for configuration control of its routing structure.

Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Abstract: Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool.

Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Abstract: An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.

Abstract: Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool.

Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Abstract: A base transistor structure and associated programmable cell library compatible with standard cell computer-aided design (CAD) tools are disclosed. In an illustrative embodiment of the invention, the base transistor structure is symmetric about one or more axes, and extends only a single grid of a standard cell CAD tool in width. The base transistor structure is advantageously configured in a manner that permits the utilization of gate isolation to separate active transistors in adjacent base transistor structures. The base transistor structure can be used to implement a programmable cell technology that is fully compatible with standard cell CAD tools.

Abstract: An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates, with each row of spare gates including multiple base transistor structures arranged adjacent to one another along longitudinal dimensions of the structures. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The spare gates may be implemented using a base transistor structure compatible with the standard cell CAD tool.

Abstract: Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool.

Abstract: A base transistor structure and associated programmable cell library compatible with standard cell computer-aided design (CAD) tools are disclosed. In an illustrative embodiment of the invention, the base transistor structure is symmetric about one or more axes, and extends only a single grid of a standard cell CAD tool in width. The base transistor structure is advantageously configured in a manner that permits the utilization of gate isolation to separate active transistors in adjacent base transistor structures. The base transistor structure can be used to implement a programmable cell technology that is fully compatible with standard cell CAD tools.

Abstract: An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates, with each row of spare gates including multiple base transistor structures arranged adjacent to one another along longitudinal dimensions of the structures. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The spare gates may be implemented using a base transistor structure compatible with the standard cell CAD tool.