Abstract: Apparatus for compressing and buffering large amounts of data, transferring the buffered data to a slower speed storage device and controlling the stopping and starting of the central processing unit (CPU) is provided for a virtual storage computer system where the data is collected in real time; the data being collected are all storage addresses to facilitate address tracing. Each real main storage address is collected to the external interface between the central processing unit (CPU) and main storage and converted to a virtual address. The virtual address is compressed and entered into a large buffer via buffer control logic. The buffer control logic sends a signal to stop the CPU when the buffer becomes full and restarts it at the exact point it had stopped after the buffer has been emptied by the transfer of data from it to a slower speed storage device.