Patents by Inventor John A. Tabler
John A. Tabler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10938352Abstract: An apparatus and methods for timing mismatch in a power amplifier includes a segmented PA with two-path timing mismatch calibration to improve ACLR performance over different signal transitions, process, voltage and temperature (PVT) variations and device aging; a fast and efficient algorithm for measuring and calibrating the delay of two paths (signal path and control path); a signal magnitude variation detection circuit, such as flash ADC, with improved comparator's performance for RF signal processing and minimum delay. A method for choosing the threshold voltage of the magnitude variation detection circuit, according to status of the signals and orthogonal frequency-division multiplexing (OFDM) related standards; other critical blocks.Type: GrantFiled: August 26, 2019Date of Patent: March 2, 2021Assignee: Vidatronic, Inc.Inventors: Jose Silva-Martinez, Junning Jiang, He Hu, John Tabler
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Patent number: 10418989Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.Type: GrantFiled: October 15, 2018Date of Patent: September 17, 2019Assignee: Exar CorporationInventors: Vinit Jayaraj, Pekka Ojala, John Tabler
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Patent number: 10389316Abstract: A silicon based (e.g., SiGe, CMOS, or BiCMOS) transmitter includes an algorithm that strategically segment and pre-distort the input signal according to its power; a reconfigurable power amplifier (PA) having a plurality of PA sections, wherein the plurality of PA sections comprise discrete weighted transistor arrays that are digitally turned OFF or ON according to a magnitude of an input signal; an impedance matching network equipped with a common-mode feedback (CMFB) mechanism configured to reduce common-mode glitches at an output of the PA due to ON/OFF manipulations of the PA segments; and a 1:N transformer, which comprises a capacitive matching engine and a power detector, disposed between the impedance matching network and the reconfigurable linear PA.Type: GrantFiled: February 19, 2019Date of Patent: August 20, 2019Assignee: Vidatronic, Inc.Inventors: Jose Silva-Martinez, Moises Robinson, Mauricio Zavaleta, John Tabler, He Hu
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Publication number: 20190052261Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.Type: ApplicationFiled: October 15, 2018Publication date: February 14, 2019Inventors: Vinit JAYARAJ, Pekka OJALA, John TABLER
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Patent number: 10103728Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.Type: GrantFiled: March 30, 2017Date of Patent: October 16, 2018Assignee: Exar CorporationInventors: Vinit Jayaraj, Pekka Ojala, John Tabler
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Publication number: 20180287604Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Inventors: Vinit JAYARAJ, Pekka OJALA, John TABLER
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Patent number: 7158841Abstract: A feedback control-loop system that employs an active DC output control circuit is disclosed which compares an input parameter measurement against a target specification associated with the input parameter measurement. In one embodiment, the active DC output control circuit receives an input signal for laser bias adjustment. In another embodiment, the active DC output control circuit receives a motor speed input from a source, such as a tachometer, for motor speed adjustment. In another embodiment, the active DC output control circuit receives an input power amplifier measurement for wireless applications.Type: GrantFiled: April 23, 2004Date of Patent: January 2, 2007Assignee: Summit Microelectronics, Inc.Inventors: Theodore M. Myers, Kenneth C. Adkins, John A. Tabler, Anurag Kaplish, Thomas J. O'Brien
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Patent number: 7002266Abstract: A control loop system is provided that employs an active DC output control circuit that more accurately calibrates the desire voltage at a load, e.g. 3.3 volts, by adjusting a trim pin on a DC/DC converter. In a first embodiment, an active DC output control circuit calibrates a DC/DC converter that is connected to a single load. In a second embodiment, an active DC output control circuit calibrates multiple DC/DC converters that are connected to multiple loads.Type: GrantFiled: November 13, 2002Date of Patent: February 21, 2006Assignee: Summit MicroelectronicsInventors: Kenneth C. Adkins, Theodore Martin Myers, John Tabler, Anurag Kaplish, Thomas J. O'Obrien
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Patent number: 6710731Abstract: Digital-to-analog converter architecture guarantees monotonicity and partial compensation for integral non-linearity. Two stages are separated by a unity-gain operational amplifier, wherein the first stage is a 1-bit resistor string-converter, having one end at reference high voltage, and the other end at reference low voltage, and the second stage is a multi-bit resistor string converter. The architecture relieves matching accuracy necessary for 1-bit front end. Resistor mismatch is compensated by varying buffer amplifier offset-voltage, and ensuring amplifier output is halfway between reference voltages; this improves integral non-linearity, or absolute accuracy, by the amount of mismatch present in the resistor string. Buffer amplifier at output of second stage of DAC controls INL error by varying offset voltage.Type: GrantFiled: September 10, 2001Date of Patent: March 23, 2004Assignee: Summit Microelectronics, Inc.Inventors: Anurag Kaplish, John A. Tabler
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Patent number: 6466149Abstract: The invention includes a segmented digital-to-analog converter (DAC) processing an N-bit input digital signal. A first segment converter processes the most significant bits and subsequent segment converters process the least significant bits of the N-bit input digital signal. The first segment converter includes ballast resistors that nullify the effect of any imbalance of the resistance of the first segment DAC versus the sum of the resistances in the remaining segment DACs. The first segment may be a 2, 4, 6, 8 or higher bit DAC while the second or subsequent segments may similarly be 2, 4, 6, 8, or higher bit DACs.Type: GrantFiled: December 29, 2000Date of Patent: October 15, 2002Assignee: Summit Microelectronics Inc.Inventor: John A. Tabler
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Publication number: 20020121995Abstract: The invention includes a segmented digital-to-analog converter (DAC) processing an N-bit input digital signal. A first segment converter processes the most significant bits and subsequent segment converters process the least significant bits of the N-bit input digital signal. The first segment converter includes ballast resistors that nullify the effect of any imbalance of the resistance of the first segment DAC versus the sum of the resistances in the remaining segment DACs. The first segment may be a 2, 4, 6, 8 or higher bit DAC while the second or subsequent segments may similarly be 2, 4, 6, 8, or higher bit DACs.Type: ApplicationFiled: December 29, 2000Publication date: September 5, 2002Applicant: SUMMIT MICROELECTRONICS, INCInventor: John A. Tabler
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Patent number: 6329856Abstract: A method and apparatus for tracking and controlling one or more voltage and current supplies during a transition between and off-state to an on-state, or from an on state to an off-state, is enabled by detecting a voltage or current transition and controlling the voltage or current supply transition within a specified upper and lower limit about a reference transition.Type: GrantFiled: August 28, 2000Date of Patent: December 11, 2001Assignee: Summit Microelectronics, Inc.Inventors: John Tabler, Kenneth C. Adkins, Theodore M. Myers, Andrew Jenkins, Warren G. Hafner