Abstract: Systems and techniques are provided for processing video data. For example, an apparatus may obtain a reference data block for predicting a block of video data and determine, using an inter-prediction processing path, one or more refined motion vectors based on the reference data block. The apparatus may perform, using the inter-prediction processing path, inter-prediction for the block of video data, wherein the inter-prediction is based on the reference data block and the one or more refined motion vectors.

Abstract: A device includes a decoder configured to identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address in a virtual address space associated with a read operation of the IBC decoding process. The target virtual address is generated according to an addressing scheme of an on-chip memory used by the IBC decoding process. The decoder is configured to identify, based on the target virtual address, an on-chip memory start address of a portion of the on-chip memory. The on-chip memory is configured to store reconstructed blocks of the video data. The decoder is also configured to perform the read operation to read a block of pixel data from the on-chip memory using the on-chip memory start address.

Abstract: A device includes a decoder configured to identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address for data access associated with a particular operation of the IBC decoding process. The target virtual address is generated according to an addressing scheme of a virtual memory used by the IBC decoding process. The decoder is configured to dynamically map the target virtual address to a particular memory address of a portion of an on-chip memory. The on-chip memory is configured to store reconstructed blocks of the video data and has a second size that is smaller than a first size of the virtual memory. The decoder is also configured to access the on-chip memory using the particular memory address to perform the particular operation of the IBC decoding process.

Abstract: A device includes a decoder configured to identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address for data access associated with a particular operation of the IBC decoding process. The target virtual address is generated according to an addressing scheme of a virtual memory used by the IBC decoding process. The decoder is configured to dynamically map the target virtual address to a particular memory address of a portion of an on-chip memory. The on-chip memory is configured to store reconstructed blocks of the video data and has a second size that is smaller than a first size of the virtual memory. The decoder is also configured to access the on-chip memory using the particular memory address to perform the particular operation of the IBC decoding process.

Abstract: Systems and techniques are provided for processing video data. For example, an apparatus may obtain a reference data block for predicting a block of video data and determine, using an inter-prediction processing path, one or more refined motion vectors based on the reference data block. The apparatus may perform, using the inter-prediction processing path, inter-prediction for the block of video data, wherein the inter-prediction is based on the reference data block and the one or more refined motion vectors.

Abstract: A method and apparatus for processing a current macro-block of a current frame for motion compensation based on reference data from a reference frame using a sliding window cache to cache the reference data are disclosed. The method steps comprise processing a current sub-block of the current macro-block for motion compensation, determining the reference data for the current sub-block based on a reference sub-block in the reference frame, determining whether the reference data is within a sliding window, if the reference data is within the sliding window, checking for a valid tag corresponding to the reference data, responsive to the valid tag, retrieving the reference data from within the sliding window cache and processing the reference data for motion compensation.

Abstract: A method and apparatus for processing a current macro-block of a current frame for motion compensation based on reference data from a reference frame using a sliding window cache to cache the reference data are disclosed. The method steps comprise processing a current sub-block of the current macro-block for motion compensation, determining the reference data for the current sub-block based on a reference sub-block in the reference frame, determining whether the reference data is within a sliding window, if the reference data is within the sliding window, checking for a valid tag corresponding to the reference data, responsive to the valid tag, retrieving the reference data from within the sliding window cache and processing the reference data for motion compensation.

Abstract: A method and apparatus are provided for scheduling data for transmission over a communication link shared by multiple applications operating on a host computer. The apparatus incorporates multiple storage components, with each storage component configured to store descriptors of data having one of multiple priorities. Each descriptor identifies a location (e.g., in host computer memory) of a portion of data to be included in a packet transmitted over the communication link. The apparatus services each storage component in turn to retrieve one or more descriptors, identify their associated data, retrieve the data and prepare it for transmission. Each storage component has an associated weight, which may be proportional to the priority of data represented by descriptors stored in the component. A storage component's weight may indicate a portion of the transmission bandwidth or a maximum amount of data that may be scheduled for transmission each time the component is serviced.

Abstract: According to the present invention, there is provided a method for determining glitch power in a logic circuit having a power supply terminal, a first input, a second input, and an output coupled to a capacitive load.