Patents by Inventor John A. Waicukauski

John A. Waicukauski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10908213
    Abstract: A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where: 1) The LTC consists of two parts that are unloaded into a tester through an output serializer. 2) The first part is unloaded per t shift cycles while the second part is unloaded once per test pattern. 3) One part of the LTC divides scan chains into groups such that X-masking effect between groups of scan chains is impossible. 4) One part of LTC divides shift cycles into groups such that X-masking effect between groups of shift cycles is impossible. Consequently, the X-masking effect in the proposed LTC is significantly reduced.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 2, 2021
    Assignee: Synopsys, Inc.
    Inventors: Emil Gizdarski, Peter Wohl, John A. Waicukauski
  • Patent number: 10346557
    Abstract: A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John Waicukauski
  • Publication number: 20180156869
    Abstract: A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 7, 2018
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John Waicukauski
  • Patent number: 9404972
    Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 2, 2016
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
  • Publication number: 20160025810
    Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Inventors: Peter Wohl, John A. Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
  • Patent number: 9171123
    Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 27, 2015
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
  • Patent number: 9157961
    Abstract: A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 13, 2015
    Assignee: Synopsys, Inc
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux, Gregory A. Maston
  • Patent number: 9152752
    Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 6, 2015
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Publication number: 20150067629
    Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
  • Publication number: 20140281774
    Abstract: A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux, Gregory A. Maston
  • Patent number: 8645780
    Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: February 4, 2014
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux
  • Publication number: 20130268817
    Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
    Type: Application
    Filed: June 5, 2013
    Publication date: October 10, 2013
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux
  • Patent number: 8549372
    Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: October 1, 2013
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Publication number: 20130232458
    Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 5, 2013
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Publication number: 20130232459
    Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.
    Type: Application
    Filed: March 5, 2012
    Publication date: September 5, 2013
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Patent number: 8464115
    Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 11, 2013
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux
  • Patent number: 8429473
    Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 23, 2013
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Publication number: 20110258503
    Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux
  • Publication number: 20110231805
    Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.
    Type: Application
    Filed: December 15, 2010
    Publication date: September 22, 2011
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Patent number: 7979763
    Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: July 12, 2011
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux