Patents by Inventor John A. Waicukauski
John A. Waicukauski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220335187Abstract: A system and method generates test patterns for simulating a circuit design. Generating the test patterns includes determining clock data of the circuit design. The clock data is determined by determining a first clock signal pair from clock signals, and determining a disturb cell based on the first clock signal pair. The disturb cell is electrically coupled to a first clock signal of the first clock signal pair, and to a second cell. The second cell is electrically coupled to a second clock signal of the first clock signal pair, and an input of the second cell is electrically coupled to an output of the disturb cell. A first test pattern is generated based on the clock data and is output to a memory to be used in simulating a circuit design.Type: ApplicationFiled: April 14, 2022Publication date: October 20, 2022Inventors: Peter WOHL, John A. WAICUKAUSKI
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Patent number: 11422186Abstract: A circuit is described that can include: a first register to store a first value that specifies a first subset of a set of scan chains, wherein the first subset of the set of scan chains includes scan cells that are desired to be masked; a second register to store a second value that specifies, in each shift cycle, a second subset of the set of scan chains, wherein the second subset of the set of scan chains includes scan cells that are desired to be masked; and a masking circuit to mask, in each shift cycle, scan cells in a third subset of the set of scan chains that is an intersection of the first subset of the set of scan chains and the second subset of the set of scan chains.Type: GrantFiled: June 19, 2020Date of Patent: August 23, 2022Assignee: Synopsys, Inc.Inventors: John A. Waicukauski, Peter Wohl
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Patent number: 10908213Abstract: A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where: 1) The LTC consists of two parts that are unloaded into a tester through an output serializer. 2) The first part is unloaded per t shift cycles while the second part is unloaded once per test pattern. 3) One part of the LTC divides scan chains into groups such that X-masking effect between groups of scan chains is impossible. 4) One part of LTC divides shift cycles into groups such that X-masking effect between groups of shift cycles is impossible. Consequently, the X-masking effect in the proposed LTC is significantly reduced.Type: GrantFiled: September 27, 2019Date of Patent: February 2, 2021Assignee: Synopsys, Inc.Inventors: Emil Gizdarski, Peter Wohl, John A. Waicukauski
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Patent number: 10346557Abstract: A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.Type: GrantFiled: March 6, 2017Date of Patent: July 9, 2019Assignee: Synopsys, Inc.Inventors: Peter Wohl, John Waicukauski
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Publication number: 20180156869Abstract: A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.Type: ApplicationFiled: March 6, 2017Publication date: June 7, 2018Applicant: Synopsys, Inc.Inventors: Peter Wohl, John Waicukauski
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Patent number: 9404972Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.Type: GrantFiled: October 5, 2015Date of Patent: August 2, 2016Assignee: Synopsys, Inc.Inventors: Peter Wohl, John A Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
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Publication number: 20160025810Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Peter Wohl, John A. Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
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Patent number: 9171123Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.Type: GrantFiled: August 30, 2013Date of Patent: October 27, 2015Assignee: Synopsys, Inc.Inventors: Peter Wohl, John A Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
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Patent number: 9157961Abstract: A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.Type: GrantFiled: March 15, 2013Date of Patent: October 13, 2015Assignee: Synopsys, IncInventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux, Gregory A. Maston
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Patent number: 9152752Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.Type: GrantFiled: March 15, 2013Date of Patent: October 6, 2015Assignee: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski
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Publication number: 20150067629Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
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Publication number: 20140281774Abstract: A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux, Gregory A. Maston
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Patent number: 8645780Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.Type: GrantFiled: June 5, 2013Date of Patent: February 4, 2014Assignee: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux
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Publication number: 20130268817Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.Type: ApplicationFiled: June 5, 2013Publication date: October 10, 2013Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux
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Patent number: 8549372Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.Type: GrantFiled: March 5, 2012Date of Patent: October 1, 2013Assignee: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski
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Publication number: 20130232459Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Applicant: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski
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Publication number: 20130232458Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.Type: ApplicationFiled: March 15, 2013Publication date: September 5, 2013Applicant: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski
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Patent number: 8464115Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.Type: GrantFiled: June 29, 2011Date of Patent: June 11, 2013Assignee: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux
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Patent number: 8429473Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.Type: GrantFiled: December 15, 2010Date of Patent: April 23, 2013Assignee: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski
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Publication number: 20110258503Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: Synopsys, Inc.Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux