Abstract: A method and apparatus for scheduling packets using a pre-sort deficit round-robin method. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. A packet is transmitted by dequeuing the packet from the pre-sorted scheduling array.

Abstract: A programmable processing system includes a first processor for executing a first portion of an instruction, a second processor for executing a second portion of the instruction, where the second portion of the instruction is interpreted by the first processor as an extension to an immediate operand field included in the first portion of the instruction.

Abstract: According to some embodiments, storage registers are provided for a processor pipeline.

Abstract: According to some embodiments, stall optimization is provided for a processor pipeline.

Abstract: In general, in one aspect, the disclosure describes a method of processing bits of a frame. The method includes accessing a subset of bits of a frame and based, at least in part, on the subset of bits, determining an address of an instruction within a set of instructions that perform at least one framing operation on the bits. The method executes instructions at the determined instruction address.

Abstract: A programmable processing system includes a first processor for executing a first portion of an instruction, a second processor for executing a second portion of the instruction, where the second portion of the instruction is interpreted by the first processor as an extension to an immediate operand field included in the first portion of the instruction.

Abstract: A processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, a processor unit executing the instructions in a pipelined fashion, a plurality of context registers for storing instructions and instruction addresses for contexts to be executed and fetch logic for selecting an address from one of the context registers and for selecting an instruction from a second of the context registers for execution substantially simultaneously for each cycle of execution of processor unit.

Abstract: A programmable processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, fetch logic for determining an address of an instruction, with the fetch logic including scheduling logic that schedules execution of the instruction contexts based on condition signals indicating an availability of a hardware resource, with the condition signals being divided into groups of condition signals, which are sampled in turn by the scheduling logic to provide a plurality of scan sets of sampled conditions.

Abstract: A Media Access Control (MAC) Bus interface definition and multiplexor scheme that may be implemented to provide chip layout-insensitive connections between a number of communication physical layer port entities and a single buffer manager or communications controller entity, utilizing a set of independent pipelined buses. The interface comprising three buses: A MAC In Data bus, a MAC Out Data bus, and a MAC Out Message bus. Each bus can operated with an independent set of timing signals to enable data transfers between a system side block and one or more network side blocks. The multiplexor scheme provides a multiplexor for each of the MAC buses, and enables a single system side block to connect to multiple network side blocks. The multiplexors may be also be cascaded.

Abstract: A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructions having a plurality of portions are issued by the instruction memory, wherein the control engine and each of the processors is caused to perform a specific task based on the portion of the instructions designated for that component. Accordingly, a data manipulation task can be divided into a plurality of subtasks that are processed in parallel by respective processing components in the architecture.

Abstract: A bi-directional data pipeline for interfacing a memory with a communications port includes a series of four pipeline elements comprising two DMA buffers and first and second holding registers. A data word is transferred from memory to the DMA buffers, each holding one data byte of the data word. With each clock cycle, the data bytes are successively transferred through the two holding registers. Two comparators are used to determine if three successive identical data bytes are present in the pipeline. If three identical bytes are detected, run length encoding is enabled, and a run length count register is incremented for each successive identical byte received through the pipeline. The run length count and associated data byte are transferred to a FIFO for transmission over the data path. A tag associated with the run length count distinguishes the run length count from data bytes in the FIFO.

Abstract: A method and arrangement for adjusting a clock frequency to allow computer devices with different clock frequencies to operate together. The arrangement scales the input clock frequency to be scaled by any desired fraction by controlling both the numerator and denominator of the scaling fraction. Clock frequency adjustment is achieved by transforming the input clock frequency into a periodic clock frequency that is reset following a desired clock period and scaling this periodic clock frequency according to a desired divisor value to generate the desired clock frequency.

Abstract: A register-based computer architecture is particularly suited for using a common resource, such as a host processor or CPU, to respond to multiple devices such as co-processors, slave processors, or peripherals via service requests initiated by these devices. The invention's register acknowledgment and service prioritizing features are preferably added to, and integrated with, a prior-art, hardware-based interrupt acknowledgment mechanism, thus providing enhanced flexibility and performance. This architecture includes features for enhancing the support of a service-request based or queue-driven interface between the host processor and the supported devices, including a Service Request Status Register, a Service Request Configuration Register, and Service Request Acknowledge Register(s). From the point of view of the host processor, these registers are accessed as normal input/output read/write operations.

Abstract: This invention provides a flexible, general-purpose, engine-based architecture for a multi-channel data communications controller. It can be customized to handle a wide range of protocols and other host system requirements with minimal reliance on the host's processing power. The always present time-critical tasks of transmitting and receiving serial data, as well as transmitting and receiving characters to/from the host, are handled quickly and efficiently by utilizing dedicated interface processors. This leaves the general purpose main engine less burdened with these time cricital tasks, enabling it to perform the relatively more complex (though less time critical) tasks of assembling and disassembling characters, as well as maintaining RAM-based data FIFOs and performing error-checking and other protocol-related tasks. Custon protocols can be implemented merely by re-microcoding the machine, without requiring modifications to the basic architecture of the chip, substantially reducing design time.

Abstract: The disclosed device uses an interconnect switch for the selective coupling of serial memory elements in series with other memory elements. A control unit may test elements, designate some of the elements as operable for use and designate other elements as spares. The memory system is defined by the states of interconnection which couple the memory elements either for operation or for sparing, and which uncouple the defective memory element from use in the system. Upon the failure of an element which is being used the control unit can switch out the defective memory cell and switch in a replacement element or simply bypass the defective element. This technique is particularly useful for wafer scale integration where a plurality of functional elements are contained on a single wafer; particularly in memory arrays which are individually addressable. However, this technique also allows the selective replacing of elements within the particular array to ensure the proper number of memory cells within the array.