Patents by Inventor John Aiton

John Aiton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor constructions comprising multi-level patterns of radiation-imageable material
    Patent number: 7535112
    Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: May 19, 2009
    Assignee: Micron Technology, Inc.
    Inventors: John Aiton, Joseph M. Richards, J. Brett Rolfson, John M. Drynan
  • Methods of forming wire bonds for semiconductor constructions
    Patent number: 7517786
    Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: April 14, 2009
    Assignee: Micron Technology, Inc.
    Inventors: John Aiton, Joseph M. Richards, J. Brett Roltson, John M. Drynan
  • Methods of forming wire bonds for semiconductor constructions
    Patent number: 7262123
    Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventors: John Aiton, Joseph M. Richards, J. Brett Rolfson, John M. Drynan
  • Semiconductor constructions comprising multi-level patterns of radiation-imageable material
    Publication number: 20070072343
    Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.
    Type: Application
    Filed: October 20, 2006
    Publication date: March 29, 2007
    Inventors: John Aiton, Joseph Richards, J. Rolfson, John Drynan
  • Methods of forming wire bonds for semiconductor constructions
    Publication number: 20060246705
    Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.
    Type: Application
    Filed: June 28, 2006
    Publication date: November 2, 2006
    Inventors: John Aiton, Joseph Richards, J. Roltson, John Drynan
  • Semiconductor constructions comprising multi-level patterns of radiation-imageable material; and methods of forming wire bonds for semiconductor constructions
    Publication number: 20060024942
    Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventors: John Aiton, Joseph Richards, J. Rolfson, John Drynan
  • Method and apparatus for focusing a wafer stepper
    Patent number: 5049925
    Abstract: A reticle for use in a wafer stepper of the type in which a lens projects the image of a mask to create a lithographically-defined pattern on a wafer. The reticle includes a plurality of parallel, opaque rectangles formed therein. The rectangles are uniform in size with the width of each rectangle bearing a ratio to the distance between adjacent rectangles of approximately 4:1.
    Type: Grant
    Filed: April 20, 1990
    Date of Patent: September 17, 1991
    Assignee: Micron Technology, Inc.
    Inventors: John Aiton, Patrick W. Vaughn, Eugene DeLarosa