Abstract: A cooking appliance includes an oven body having an interior compartment and a door panel for accessing the interior compartment, wherein the interior compartment is sized to receive a food product; a removable heated tray positionable within the interior compartment, wherein the heated tray includes a top tray surface and a first heating source positioned below the top tray surface; and a second heating source positioned within the interior compartment.

Abstract: A check valve assembly for a drain pump configured to transfer fluid from a sump, through a volute having a pump discharge passageway extending from the volute, includes a seat assembly and a flapper assembly. The seat assembly has a body with a first distal end and a second distal end, and a fluid passage extending through the body. The body defines a valve seat having a sealing surface about the fluid passage. The flapper assembly is operably coupled to the seat assembly. The flapper assembly has a moveable portion configured to selectively move between a closed position where the moveable portion seals against the sealing surface and an opened position where the moveable portion raises to allow liquid through the fluid passage. The check valve assembly is configured to be located within the pump discharge passageway.

Abstract: A check valve assembly for a drain pump configured to transfer fluid from a sump, through a volute having a pump discharge passageway extending from the volute, includes a seat assembly and a flapper assembly. The seat assembly has a body with a first distal end and a second distal end, and a fluid passage extending through the body. The body defines a valve seat having a sealing surface about the fluid passage. The flapper assembly is operably coupled to the seat assembly. The flapper assembly has a moveable portion configured to selectively move between a closed position where the moveable portion seals against the sealing surface and an opened position where the moveable portion raises to allow liquid through the fluid passage. The check valve assembly is configured to be located within the pump discharge passageway.

Abstract: A dishwasher having a tub, a sump fluidly coupled to the tub, a discharge outlet, a drain assembly, and a check valve drain assembly including a seat assembly having a body with a first distal end and a second distal end, a fluid passage extending through the body, the body defining a valve seat having a sealing surface about the fluid passage and a flapper assembly operably coupled to the seat assembly and having a moveable portion configured to selectively move between a closed position where the moveable portion seals against the sealing surface and an opened position where the moveable portion raises to allow liquid through the fluid passage.

Abstract: A dishwasher includes a tub at least partially defining a treating chamber with an access opening, a sump fluidly coupled to the treating chamber, at least one sprayer emitting liquid into the treating chamber, a pump, a conduit fluidly coupling the sump to the pump and the pump to the at least one sprayer, thereby defining a recirculation circuit through which the liquid sprayed into the treating chamber collects in the sump and is pumped back to the at least one sprayer, a filter assembly provided in the sump and having a filter through which at least a portion of the liquid passes, and an insert sleeve at least partially located within the filter assembly.

Abstract: A dishwasher having a tub, a sump fluidly coupled to the tub, a discharge outlet, a drain assembly, and a check valve drain assembly including a seat assembly having a body with a first distal end and a second distal end, a fluid passage extending through the body, the body defining a valve seat having a sealing surface about the fluid passage and a flapper assembly operably coupled to the seat assembly and having a moveable portion configured to selectively move between a closed position where the moveable portion seals against the sealing surface and an opened position where the moveable portion raises to allow liquid through the fluid passage.

Abstract: A dishwasher includes a tub at least partially defining a treating chamber with an access opening, a sump fluidly coupled to the treating chamber, at least one sprayer emitting liquid into the treating chamber, a pump, a conduit fluidly coupling the sump to the pump and the pump to the at least one sprayer, thereby defining a recirculation circuit through which the liquid sprayed into the treating chamber collects in the sump and is pumped back to the at least one sprayer, a filter assembly provided in the sump and having a filter through which at least a portion of the liquid passes, and an insert sleeve at least partially located within the filter assembly.

Abstract: A method and apparatus for combining micro-operations to process immediate data. The immediate data may be wider than the immediate data storage capacity of a micro-operation. A first micro-operation is issued to process a first portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. A second micro-operation is issued to process a second portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. Execution of the first and second micro-operations and optionally of a third micro-operation serves to reconstruct the immediate data comprising the first portion and the second portion of the immediate data.

Abstract: The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.

Abstract: The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.

Abstract: The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.

Abstract: A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.

Abstract: In a processing core, a newly received load instruction may be dependent upon a previously received store instruction. The core may include a predictor to predict such dependencies and provide an identification of a colliding store instruction. The load instruction may be stored in a scheduler with a dependency marker. Thereafter, the load instruction may be prevented from executing until after execution of the colliding store. Upon execution of the load, the accuracy of the prediction is confirmed. Upon retirement of the load instruction, new prediction results may be provided to the predictor.

Abstract: Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out of a trace cache, and accessing an entry in a global history with repeatable variations of a stew when there is more than branch instruction within a trace within the trace cache and at least a second branch instruction is read out.

Abstract: A method and apparatus for representing an address in canonical form. The address is received and an error indicator is computed according to whether the address is received in a correct canonical form. The error indicator is stored together with a portion of the address, the portion being less than the entire address. The error indicator, together with the portion of the address stored, represent the address received.

Abstract: An instruction pipeline in a microprocessor includes one or more of the pipelines maintaining a return buffer. Upon detecting a call instruction, a pipeline will push the return address onto its return buffer. The pipeline will then determine if the call instruction was detected by a second pipeline and will send the return address to the second pipeline if the call was not detected by the second pipeline. Upon detecting a return instruction, the pipeline will pop the return address at the top of its return buffer. The return address may then be used in the instruction pipeline. The pipeline will send a request to a third pipeline to fill its return buffer with entries from the third pipeline's return buffer. The pipeline will determine if the return instruction was detected by a second pipeline and will send the return address at the top of its return buffer to the second pipeline if the return was not detected by the second pipeline.

Abstract: A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.

Abstract: An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of which having multiple entries that may include predicted return addresses that have been pushed onto the return buffer.

Abstract: A microprocessor includes a first memory to store microcode and a second memory to store predicted micro-operation addresses. Micro-operation addresses are predicted, stored in memory, and retrieved to get the next micro-operations from the microcode memory. Misprediction recovery logic is used to determine if the next predicted address is correct and to determine a recovery address to correct the predicted address if the predicted address is incorrect.

Abstract: Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out of a trace cache, and accessing an entry in a global history with repeatable variations of a stew when there is more than branch instruction within a trace within the trace cache and at least a second branch instruction is read out.