Abstract: A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

Abstract: A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

Abstract: A method stores data and check bits for that data within a memory chip. The memory chip stores the data and check bits in a plurality of pages contained in the memory chip, each page including a plurality of storage locations with each storage location having an associated address. The method includes receiving data to be stored in the memory, calculating check bits for the received data, mapping the data to addresses associated with the storage locations in a given page in the memory chip, mapping the check bits to addresses associated with the storage locations contained in the same page as the data, and storing the data and check bits in the page. The method may be applied to a single memory chip or to multiple memory chips.

Abstract: A method and apparatus using a set of registers for indicating multiple error levels in a data processing system, wherein a register allows software to reprogram or redefine the error level to another desired error level. One embodiment of the invention involves a method for indicating errors in a data processing system with multiple error levels, indicating that an error corresponds to one of the multiple error levels, representing the error with a set of memory cells, and changing the error level of the error to another error level of the multiple error levels. A second embodiment of the invention involves a data processing system or an error log system, having an associated error level chosen from a plurality of error levels for an error. The data processing system or error log system includes a set of memory cells, with a primary error log to record the error, at least one error enable register that can be read and written to redefine the error level of the error to one of said plurality of error levels.

Abstract: One embodiment relates to a method of switching by a crossbar switch having a plurality of ports. The method includes transmitting data from a transmit port to a first receive port across the crossbar switch, receiving a control message at the transmit port to be sent to a second receive port, suspending the data transmission from the transmit port to the first receive port, transmitting the control message from the transmit port to the second receive port, and resuming the data transmission from the transmit port to the first receive port. Another embodiment relates to a crossbar switching system. The system includes circuitry at a transmit port for providing a data transfer mode and a data suspension mode.