Patents by Inventor John Albrecht Ott
John Albrecht Ott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7550369Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal.Type: GrantFiled: October 17, 2007Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Joel Pereira de Souza, Keith Edward Fogel, John Albrecht Ott, Devendra Kumar Sadana, Katherine Lynn Saenger
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Publication number: 20090026459Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.Type: ApplicationFiled: June 27, 2008Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack Oon Chu, Basanth Jaqannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
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Patent number: 7285473Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal.Type: GrantFiled: January 7, 2005Date of Patent: October 23, 2007Assignee: International Business Machines CorporationInventors: Joel Pereira de Souza, Keith Edward Fogel, John Albrecht Ott, Devendra Kumar Sadana, Katherine Lynn Saenger
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Patent number: 7183576Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.Type: GrantFiled: February 10, 2004Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Basanth Jagannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
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Patent number: 6908866Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.Type: GrantFiled: February 10, 2004Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Basanth Jagannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
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Patent number: 6805962Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diffusion of Ge. Optionally forming a Si cap layer over the SiGe or pure Ge layer, and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer, the optional Si cap and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate materials are also disclosed herein.Type: GrantFiled: January 23, 2002Date of Patent: October 19, 2004Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Jack O. Chu, Keith E. Fogel, Steven J. Koester, Devendra K. Sadana, John Albrecht Ott
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Publication number: 20040161875Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm−3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.Type: ApplicationFiled: February 10, 2004Publication date: August 19, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack Oon Chu, Basanth Jagannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
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Publication number: 20040161911Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm−3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.Type: ApplicationFiled: February 10, 2004Publication date: August 19, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack Oon Chu, Basanth Jagannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
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Patent number: 6750119Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm−3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.Type: GrantFiled: April 20, 2001Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Basanth Jagannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
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Patent number: 6524935Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1−yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC.Type: GrantFiled: September 29, 2000Date of Patent: February 25, 2003Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Jack Oon Chu, Christopher P. D'Emic, Lijuan Huang, John Albrecht Ott, Hon-Sum Philip Wong
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Publication number: 20020182423Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm−3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.Type: ApplicationFiled: April 20, 2001Publication date: December 5, 2002Applicant: International Business Machines CorporationInventors: Jack Oon Chu, Basanth Jagannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
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Patent number: 6475072Abstract: A method and apparatus is described incorporating a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool. The CMP is performed with a down force of 1 psi, a backside air pressure of 0.5 psi, a platen speed of 50 rpm, a crarrier speed of 30 rpm and a slurry flow rate of 140 milliliters per minute.Type: GrantFiled: September 29, 2000Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Jack Oon Chu, Guy M. Cohen, Lijuan Huang, John Albrecht Ott, Michael F. Lofaro
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Patent number: 6251751Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.Type: GrantFiled: April 13, 1999Date of Patent: June 26, 2001Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid Ezzeldin Ismail, Kim Yang Lee, John Albrecht Ott
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Patent number: 5963817Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.Type: GrantFiled: October 16, 1997Date of Patent: October 5, 1999Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid Ezzeldin Ismail, Kim Yang Lee, John Albrecht Ott