Patents by Inventor John Alexander Young
John Alexander Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147867Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.Type: ApplicationFiled: October 31, 2022Publication date: May 2, 2024Applicant: Intel CorporationInventors: Punyashloka Debashis, Dominique A. Adams, Hai Li, Chia-Ching Lin, Dmitri Evgenievich Nikonov, Kaan Oguz, John J. Plombon, Ian Alexander Young
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Publication number: 20240120415Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.Type: ApplicationFiled: October 1, 2022Publication date: April 11, 2024Applicant: Intel CorporationInventors: Scott B. Clendenning, Sudarat Lee, Kevin P. O'Brien, Rachel A. Steinhardt, John J. Plombon, Arnab Sen Gupta, Charles C. Mokhtarzadeh, Gauri Auluck, Tristan A. Tronic, Brandon Holybee, Matthew V. Metz, Dmitri Evgenievich Nikonov, Ian Alexander Young
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Publication number: 20240113212Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Hai Li, Arnab Sen Gupta, Gauri Auluck, I-Cheng Tung, Brandon Holybee, Rachel A. Steinhardt, Punyashloka Debashis
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Publication number: 20240113220Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Arnab Sen Gupta, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Uygar E. Avci, Kevin P. O'Brien, Scott B. Clendenning, Jason C. Retasket, Shriram Shivaraman, Dominique A. Adams, Carly Rogan, Punyashloka Debashis, Brandon Holybee, Rachel A. Steinhardt, Sudarat Lee
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Publication number: 20240105822Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and theType: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Kevin P. O'Brien, Brandon Holybee, Carly Rogan, Dmitri Evgenievich Nikonov, Punyashloka Debashis, Rachel A. Steinhardt, Tristan A. Tronic, Ian Alexander Young, Marko Radosavljevic, John J. Plombon
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Publication number: 20240105810Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Rachel A. Steinhardt, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Arnab Sen Gupta, Brandon Holybee, Punyashloka Debashis, I-Cheng Tung, Gauri Auluck
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Publication number: 20240097031Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Applicant: Intel CorporationInventors: Punyashloka Debashis, Rachel A. Steinhardt, Brandon Holybee, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Ian Alexander Young, Raseong Kim, Carly Rogan, Dominique A. Adams, Arnab Sen Gupta, Marko Radosavljevic, Scott B. Clendenning, Gauri Auluck, Hai Li, Matthew V. Metz, Tristan A. Tronic, I-Cheng Tung
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Patent number: 11042613Abstract: A first set of device usage characteristics of a first user interaction with a user communication device are received. For example, a device usage characteristic may be an average key pressure, a used WiFi access point, an install date of an application, an angle of a user communication device, etc. The first set of device usage characteristics of the first user interaction are compared to a second set of device usage characteristics of a second user interaction with the user communication device that is stored in a blockchain. One or more reason codes that identifies why the first and second compared sets of device usage characteristics do not match is generated in response to the first and second compared sets of device usage characteristics not matching. The one or more reason codes are used for identifying a level of trust of a user in a communication session.Type: GrantFiled: October 30, 2018Date of Patent: June 22, 2021Assignee: Avaya Inc.Inventors: Pushkar Yashavant Deole, John Alexander Young
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Publication number: 20200134143Abstract: A first set of device usage characteristics of a first user interaction with a user communication device are received. For example, a device usage characteristic may be an average key pressure, a used WiFi access point, an install date of an application, an angle of a user communication device, etc. The first set of device usage characteristics of the first user interaction with the user communication device are compared to a second set of device usage characteristics of a second user interaction with the user communication device that is stored in a blockchain. One or more reason codes that identifies why the first and second compared sets of device usage codes do not match is generated in response to the first and second compared sets of device usage characteristics not matching. The one or more reason codes are used for identifying a level of trust of a user in a communication session.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Inventors: Pushkar Yashavant Deole, John Alexander Young
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Publication number: 20200125704Abstract: Embodiments of the disclosure provide a communication system and method. In one example, the communication system is disclosed to include a communication device configured for use by a primary user and a borrowing user, where use of the communication device by the primary user is governed by primary user permissions, and where use of the communication device by a borrowing user is governed by borrowing user permissions. The illustrative system is further disclosed to include computer memory having a set of user binding instructions that, when executed by a processor, enable establishment of a binding relationship between the communication device and the primary user and, so long as the binding relationship between the communication device and the primary user is maintained, enable use of the communication device to be governed by the primary user permissions instead of the borrowing user permissions.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventors: David Chavez, Pushkar Yashavant Deole, John Alexander Young, Yolanda Del Toro
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Patent number: 6522738Abstract: A system for facilitating the administration of a network accessible file stored on a network computer by means of communication with a user over a telephone handset. The network computer storing the network accessible file, typically a Hypertext Markup Language (HTML) file for use in a web site, allows a user to dial in and, through the use of a telephone handset, modify, create, delete or exchange web pages comprising the web site. The network computer presents the user with a list of modifiable objects contained in a web page, through speech simulation software, and receives instructions identifying and modifying these objects by speech or Dual Tone MultiFrequency (DTMF) tones. Upon receipt of these instructions, the network computer generates a new HTML file to replace the modified HTML file.Type: GrantFiled: December 16, 1998Date of Patent: February 18, 2003Assignee: Nortel Networks LimitedInventors: Brian Cruickshank, John Alexander Young