Abstract: A system, method, and apparatus for performing hardware-based cryptographic operations are disclosed. The apparatus can include an encryption device with a hardware accelerator having an accumulator, a multiplier circuit, an adder circuit, and a state machine. The state machine can control successive operation of the hardware accelerator to carry out a rapid, multiplier-based reduction of a large integer by a prime modulus value. Optionally, the hardware accelerator can include a programmable logic device such as a field-programmable gate array with one or more dedicated multiple-accumulate blocks.

Abstract: A cryptographic switch for routing information is disclosed. The cryptographic switch includes a first and second input ports, a first and second output ports and a first and second cryptographic paths. The first cryptographic path is configured to programmably couple between at least one of the first or second input ports and at least one of the first or second output ports. The second cryptographic path is configured to programmably couple between at least one of the first or second input ports and at least one of the first or second output ports.