Abstract: A method of creating a layout of high speed logic includes extracting dimensions of logic elements from a logic element library. A first logic element is placed in the layout and a second logic element is placed relative to the first logic element. The second logic element is placed according to a relative placement attribute. Additional logic elements are autoplaced according to the logic design. Interconnect is then autorouted between the logic elements according to the logic design. In many embodiments, the second logic element is placed by adding a dimension of the first logic element and an offset specified by the relative placement attribute to the location of the first logic element. In embodiments, components may contain hierarchy with relatively placed logic elements within them. In these embodiments, a minimum dimension for a first component is computed from logic element dimensions and placements within the component.

Abstract: An IC layout design process and system involves placing an adjustable capacitor cell having a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape. The polysilicon shapes are electrically coupled to a first power rail and the active area shapes are electrically coupled to a second power rail. The sub-cells of the adjustable capacitor cell are operable to be modified to satisfy a density measurement associated with the IC's fabrication flow.

Abstract: An IC layout design process and system involves placing an adjustable capacitor cell having a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape. The polysilicon shapes are electrically coupled to a first power rail and the active area shapes are electrically coupled to a second power rail. The sub-cells of the adjustable capacitor cell are operable to be modified to satisfy a density measurement associated with the IC's fabrication flow.