Abstract: A digital detection system for binary differential phase shift keyed (DPSK) signals includes first and second multipliers to which the signal is applied, and which receive reference signals applied in quadrature to the two multipliers. The outputs of the multipliers are each applied through a filter to a one bit delay circuit, with the outputs of the filters and delay circuits being applied to third and fourth multipliers. The outputs of the third and fourth multipliers which receive signals from the two filters are summed to provide the detected digital signal. The filters may be matched filters each including an integrate, sample and dump circuit, and a data transition tracking loop coupled to the first multiplier and to the detector system output provides a bit synchronization signal for the matched filters. An I-Q loop may be coupled to the outputs of the two matched filters and controls an oscillator which provides the reference signals for the first and second multipliers.