Patents by Inventor John August Orlowski
John August Orlowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11765826Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: GrantFiled: January 25, 2021Date of Patent: September 19, 2023Assignee: Qorvo US, Inc.Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Patent number: 11596058Abstract: Laminate structures and configurations of fiducials for laminates structures for electronic devices are disclosed. Fiducials are formed in laminate structures to provide increased visibility and contrast, thereby improving detection of the fiducials with optical detection equipment of automated machines commonly used in the electronics industry. Fiducials are disclosed that are defined by openings in laminate structures that extend to depths within the laminate structures to provide sufficient contrast. Openings for fiducials may be arranged to extend through multiple metal layers and dielectric layers of the laminate structures. The fiducials may be formed by laser drilling or other subtractive processing techniques.Type: GrantFiled: April 15, 2019Date of Patent: February 28, 2023Assignee: Qorvo US, Inc.Inventors: John August Orlowski, Stephen Craig Parker, James Edwin Culler, Jr.
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Patent number: 11244786Abstract: This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.Type: GrantFiled: August 29, 2019Date of Patent: February 8, 2022Assignee: Qorvo US, Inc.Inventors: Dirk Robert Walter Leipold, George Maxim, John August Orlowski, Baker Scott
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Patent number: 11094459Abstract: This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.Type: GrantFiled: August 20, 2019Date of Patent: August 17, 2021Assignee: Qorvo US, Inc.Inventors: Dirk Robert Walter Leipold, George Maxim, John August Orlowski, Baker Scott
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Publication number: 20210144853Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: ApplicationFiled: January 25, 2021Publication date: May 13, 2021Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Patent number: 10905007Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: GrantFiled: January 8, 2020Date of Patent: January 26, 2021Assignee: Qorvo US, Inc.Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Publication number: 20210007224Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: ApplicationFiled: January 8, 2020Publication date: January 7, 2021Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Patent number: 10796835Abstract: Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.Type: GrantFiled: July 13, 2016Date of Patent: October 6, 2020Assignee: Qorvo US, Inc.Inventors: Michael F. Zybura, George Maxim, Dirk Robert Walter Leipold, John August Orlowski, Baker Scott
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Publication number: 20200288567Abstract: Laminate structures and configurations of fiducials for laminates structures for electronic devices are disclosed. Fiducials are formed in laminate structures to provide increased visibility and contrast, thereby improving detection of the fiducials with optical detection equipment of automated machines commonly used in the electronics industry. Fiducials are disclosed that are defined by openings in laminate structures that extend to depths within the laminate structures to provide sufficient contrast. Openings for fiducials may be arranged to extend through multiple metal layers and dielectric layers of the laminate structures. The fiducials may be formed by laser drilling or other subtractive processing techniques.Type: ApplicationFiled: April 15, 2019Publication date: September 10, 2020Inventors: John August Orlowski, Stephen Craig Parker, James Edwin Culler, JR.
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Publication number: 20190385791Abstract: This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Dirk Robert Walter Leipold, George Maxim, John August Orlowski, Baker Scott
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Publication number: 20190371523Abstract: This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.Type: ApplicationFiled: August 20, 2019Publication date: December 5, 2019Inventors: Dirk Robert Walter Leipold, George Maxim, John August Orlowski, Baker Scott
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Patent number: 10483035Abstract: This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.Type: GrantFiled: August 30, 2016Date of Patent: November 19, 2019Assignee: Qorvo US, Inc.Inventors: Dirk Robert Walter Leipold, George Maxim, John August Orlowski, Baker Scott
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Patent number: 10043707Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.Type: GrantFiled: March 26, 2013Date of Patent: August 7, 2018Assignee: Qorvo US, Inc.Inventors: John August Orlowski, David Jandzinski
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Publication number: 20170084379Abstract: This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.Type: ApplicationFiled: August 30, 2016Publication date: March 23, 2017Inventors: Dirk Robert Walter Leipold, George Maxim, John August Orlowski, Baker Scott
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Publication number: 20170084378Abstract: This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.Type: ApplicationFiled: August 30, 2016Publication date: March 23, 2017Inventors: Dirk Robert Walter Leipold, George Maxim, John August Orlowski, Baker Scott
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Publication number: 20170062119Abstract: Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.Type: ApplicationFiled: July 13, 2016Publication date: March 2, 2017Inventors: Michael F. Zybura, George Maxim, Dirk Robert Walter Leipold, John August Orlowski, Baker Scott
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Publication number: 20150201515Abstract: An electronics module includes a non-conductive body, a first set of conductive features exposed on a surface of the non-conductive body, and a second set of conductive features exposed on the surface of the non-conductive body. The first set of conductive features is configured to connect to a wire bond component. The second set of conductive features is configured to connect to a flip chip component. A protective finish is provided over each one of the first set of conductive features and the second set of conductive features. The protective finish includes a layer of nickel less than 1 ?m thick, a layer of palladium over the layer of nickel, and a layer of gold over the layer of palladium.Type: ApplicationFiled: January 13, 2015Publication date: July 16, 2015Inventors: Donald Joseph Leahy, Jungwoo Lee, John August Orlowski, Howard Joseph Holyoak
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Publication number: 20140146489Abstract: An electronic substrate includes a non-conductive body and one or more conductive features coupled to the non-conductive body. Each of the conductive features includes a base layer. To preserve the performance and conductivity of the one or more conductive features, each of the conductive features includes a protective layer formed over the base layer. The protective layer may include a first layer of silver formed over the base layer and a second layer of palladium formed over the first layer. By depositing the protective layer over the base layer of each of the conductive features, oxidation and exposure of the conductive features is prevented, or at least substantially reduced, since the first layer and the second layer provide a migration barrier for the metal in the base layer. However, the performance and conductivity of the conductive features are maintained due to the low resistivity of silver and palladium.Type: ApplicationFiled: May 10, 2013Publication date: May 29, 2014Inventors: John August Orlowski, Donald Joseph Leahy, Thomas Scott Morris, David C. Dening, David Jandzinski
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Publication number: 20140144682Abstract: An electronic substrate includes one or more conductive features. In order to preserve the performance and conductivity of the one or more conductive features, the exposed portions of the conductive features are deposited with a protective layer comprising a layer of silver, followed by a layer of gold. By covering the exposed portions of the conductive features of the electronic substrate with the protective layer, oxidation and exposure of the conductive features is prevented, thereby preserving the performance and conductivity of the copper features. Further, during a soldering process, the protective layer is substantially dissolved, thereby allowing the solder to join directly with the underlying conductive features and improving the performance of the electronic substrate.Type: ApplicationFiled: May 10, 2013Publication date: May 29, 2014Applicant: RF Micro Devices, Inc.Inventors: John August Orlowski, Donald Joseph Leahy
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Publication number: 20140106564Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.Type: ApplicationFiled: March 26, 2013Publication date: April 17, 2014Applicant: RF Micro Devices, Inc.Inventors: John August Orlowski, David Jandzinski