Abstract: An improved clock generation circuit is provided that operates with a single input clock frequency, and includes a Phase Locked Loop circuit (PLL) with a digital accumulator in the feedback loop, in which either the Most Significant Bit or the Carry Bit of the binary adder is used as the modulated feedback clock to the phase/frequency detector of the PLL. In one embodiment, a fixed add/phase amount is used to drive one of the inputs of the binary adder to generate a fixed output frequency. If it is desired to modulate the output frequency, then an Add Amount Modulator circuit can be provided that presents a varying numeric value to one of the inputs of the binary adder. The MSB or Carry Bit is communicated to an address look-up table, which then outputs an address to a memory circuit, which in turn presents a different add amount to the binary adder.