Abstract: A new planar, fully ion-implanted indium phosphide junction FET (JFET) fabrication process, utilizing n.sup.+ source-drain implantation, Be and Be/P p.sup.+ gate implantation, and nitride-registered gate metallization.

Abstract: A low metal resistance ohmic contact alloyed to p InP material having TiW within the contact as a diffusion barrier layer between an underlay of AuZn and an overlay of Au. A process for fabricating an InP JFET containing a gate contact of respective AuZn, TiW, and Au layers and with the gate contact alloyed to p InP material of a semiconductive gate region provides an improved InP JFET having a low resistance metal alloyed ohmic contact to the gate region. Use of the TiW layer in a multilayer contact alloyed to P InP material leads to unique processing and improved InP semiconductor devices.

Abstract: An integrated, planar, single-channel, photodetector-amplifier device is disclosed. The single-channel device includes a photodetector layer and an amplifier layer above the photodetector layer. The photodetector layer is low-doped to give a low dark current and is sufficiently thick to give a high quantum efficiency. The amplifier layer is of a smaller thickness and is a more highly doped material than the photodetector layer, to provide an amplifier having high gain. An insulating layer is included between the photodetector and amplifier layers for electrically isolating the photodetector and amplifier layers. The layers are fabricated on a substrate. Isolation regions are also included for electrically laterally isolating a photodetector, amplifier, and other circuit components comprising the single channel device from each other.

Abstract: A low metal resistance ohmic contact alloyed to p InP material having TiW within the contact as a diffusion barrier layer between an underlay of AuZn and an overlay of Au. A process for fabricating an InP JFET containing a gate contact of respective AuZn, TiW, and Au layers and with the gate contact alloyed to p InP material of a semiconductive gate region provides an improved InP JFET having a low resistance metal alloyed ohmic contact to the gate region. Use of the TiW layer in a multilayer contact alloyed to p InP material leads to unique processing and improved InP semiconductor devices.

Abstract: A method of making a planar junction field-effect transistor in which a semi-insulating substrate of a III-V semiconductor, particularly InP, is ion implanted by two ions to produce both an n-type region and a p-type region. The gate is further defined by selectively etching through the gate-implant region to the source/drain channel.