Abstract: A two-stage switching network is provided wherein the two stages are interconnected by a pseudo space switch. The input and output ports of the network, each comprising a plurality of channels, are partitioned into groups each one of which is common to a time division switch. Each switch comprises a serial-to-parallel or a parallel-to-serial converter circuit, a data memory and a connection memory. The space switch comprises a commutator circuit for sequentially and periodically connecting each of the input switches to each of the output switches once for each channel. The commutator comprises a plurality of layers corresponding in number to the number of bits in each PCM word.