Patents by Inventor John B. Conrad
John B. Conrad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9874925Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: GrantFiled: December 11, 2015Date of Patent: January 23, 2018Assignee: Intel CorporationInventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Patent number: 9870044Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: GrantFiled: September 29, 2016Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20170269672Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: December 11, 2015Publication date: September 21, 2017Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20170017297Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: September 29, 2016Publication date: January 19, 2017Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20160098075Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Patent number: 9235258Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: GrantFiled: April 16, 2014Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Patent number: 9223389Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: GrantFiled: September 25, 2014Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Patent number: 9223390Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: GrantFiled: September 25, 2014Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20150058667Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: September 25, 2014Publication date: February 26, 2015Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20150052377Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: September 25, 2014Publication date: February 19, 2015Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20150006938Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: April 16, 2014Publication date: January 1, 2015Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Patent number: 8707062Abstract: For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.Type: GrantFiled: February 16, 2010Date of Patent: April 22, 2014Assignee: Intel CorporationInventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20130013945Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20120072750Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: August 29, 2011Publication date: March 22, 2012Inventors: Sanjeev Jahagirdar, Vargbese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Publication number: 20100146311Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: ApplicationFiled: February 16, 2010Publication date: June 10, 2010Applicant: Intel CorporationInventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Patent number: 7664970Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.Type: GrantFiled: December 30, 2005Date of Patent: February 16, 2010Assignee: Intel CorporationInventors: Sanjeev Jahagirdar, George Varghese, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Navch, Shai Rotem
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Patent number: 7299370Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.Type: GrantFiled: June 10, 2003Date of Patent: November 20, 2007Assignee: Intel CorporationInventors: Varghese George, Mark A. Newman, Sanjeev Jahagirdar, Inder M. Sodhi, Tanjeer R. Khondker, Mathew B. Nazareth, John B. Conrad
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Publication number: 20040255176Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.Type: ApplicationFiled: June 10, 2003Publication date: December 16, 2004Inventors: Varghese George, Mark A. Newman, Sanjeev Jahagirdar, Inder M. Sodhi, Tanveer R. Khondker, Mathew B. Nazareth, John B. Conrad