Abstract: A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

Abstract: A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.

Abstract: A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.

Abstract: A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.

Abstract: A system including an integrated circuit memory device. The integrated circuit device comprises a register to store a value representative of an output voltage setting. A circuit holds a value representative of an adjustment to the output voltage setting. An output driver outputs a drive voltage during a calibration operation, wherein a signal is generated based on a comparison between a signal derived from the drive voltage and a reference voltage. The signal updates the value representative of the adjustment to the output voltage setting.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: A method and apparatus for an integrated circuit package is provided. The integrated circuit package is designed for coupling an integrated circuit to a printed circuit board. The integrated circuit package includes a base having a bottom and a side. A flex circuit having traces therein is coupled to the base. The traces in the flex circuit are designed to couple to the leads of the integrated circuit. The traces further are designed to couple to traces on the printed circuit board.