Abstract: An example balun includes a center conductor that passes through a printed wiring board having multiple dielectric layers and cage vias arranged relative to the center conductor. The cage vias include a first set of cage vias that extend between an unbalanced connection to the balun and a balanced connection to the balun. The first set of cage vias are part of a first circular arc and are connected to electrical ground through a first ground ring. The cage vias include a second set of cage vias that extend from the unbalanced connection part-way through the printed wiring board. The second set of cage vias are part of a second circular arc and are connected to the electrical ground through a second ground ring. The second circular arc is longer than the first circular arc.

Abstract: An example balun includes a center conductor that passes through a printed wiring board having multiple dielectric layers and cage vias arranged relative to the center conductor. The cage vias include a first set of cage vias that extend between an unbalanced connection to the balun and a balanced connection to the balun. The first set of cage vias are part of a first circular arc and are connected to electrical ground through a first ground ring. The cage vias include a second set of cage vias that extend from the unbalanced connection part-way through the printed wiring board. The second set of cage vias are part of a second circular arc and are connected to the electrical ground through a second ground ring. The second circular arc is longer than the first circular arc.

Abstract: A coaxial transmission line structure having a center conductor section having an input contact and an output contact the output contact being larger than the input contact, the center conductor having a plurality of different geometrically shaped, electrically conductive layers having sizes progressively increasing from the input contact to the larger output contact to conductor transition from the input contact to the larger output contact, the electrically conductive layers being electrically interconnected by staggered microvias passing through dielectric layers to the center, and (B) an outer conductor section disposed about, coaxial with, and electrically isolated from, the center conductor by the dielectric layers.

Abstract: A coaxial transmission line structure having a center conductor section having an input contact and an output contact the output contact being larger than the input contact, the center conductor having a plurality of different geometrically shaped, electrically conductive layers having sizes progressively increasing from the input contact to the larger output contact to conductor transition from the input contact to the larger output contact, the electrically conductive layers being electrically interconnected by staggered microvias passing through dielectric layers to the center, and (B) an outer conductor section disposed about, coaxial with, and electrically isolated from, the center conductor by the dielectric layers.

Abstract: An radio-frequency (RF) interposer enables low-cost, high-performance RF interconnection of two or more large-area printed wiring boards (PWBs). The RF interposer may be provided as a multi-port coaxial structure embedded in a metal (or metalized) carrier. The RF interposer may include one or more conductive shims having spring fingers to provide contact across air-gaps between a PWB RF ground plane and a ground plane of the RF interposer. Retractable pins may be used as the coaxial transmission line center conductors. The RF interposer may be provided as an N×M grid of unit cells each having one or more RF ports and a cavities to provide clearance for a PWB component.

Abstract: An radio-frequency (RF) interposer enables low-cost, high-performance RF interconnection of two or more large-area printed wiring boards (PWBs). The RF interposer may be provided as a multi-port coaxial structure embedded in a metal (or metalized) carrier. The RF interposer may include one or more conductive shims having spring fingers to provide contact across air-gaps between a PWB RF ground plane and a ground plane of the RF interposer. Retractable pins may be used as the coaxial transmission line center conductors. The RF interposer may be provided as an N×M grid of unit cells each having one or more RF ports and a cavities to provide clearance for a PWB component.

Abstract: A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components.

Abstract: Embodiments of the concepts described herein are directed toward a common RF building block in the form of a monolithic assembly for an AESA array featuring a scalable RF design based on 2n:3 combining. The monopulse network building blocks are substantially identical, enabling an interchangeable sub-array architecture that is independent of position in the AESA aperture and receive sum channel sidelobe performance. In one embodiment, a passive Monopulse Beamformer may provide the passive 2n:3 RF coupling/combining network and an active Monopulse Processor may perform amplitude and phase weighting for the combined signals from the Monopulse Beamformer.

Abstract: In one aspect, an active electronically scanned array (AESA) card includes a printed wiring board (PWB) that includes a first set of metal layers used to provide RF signal distribution, a second set of metal layers used to provide digital logical distribution, a third set of metal layers used to provide power distribution and a fourth set of metal layers used to provide RF signal distribution. The PWB comprises at least one transmit/receive (T/R) channel used in an AESA.

Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.

Abstract: A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components.

Abstract: Embodiments of the concepts described herein are directed toward a common RF building block in the form of a monolithic assembly for an AESA array featuring a scalable RF design based on 2n:3 combining. The monopulse network building blocks are substantially identical, enabling an interchangeable sub-array architecture that is independent of position in the AESA aperture and receive sum channel sidelobe performance. In one embodiment, a passive Monopulse Beamformer may provide the passive 2n:3 RF coupling/combining network and an active Monopulse Processor may perform amplitude and phase weighting for the combined signals from the Monopulse Beamformer.

Abstract: In one aspect, an active electronically scanned array (AESA) card includes a printed wiring board (PWB) that includes a first set of metal layers used to provide RF signal distribution, a second set of metal layers used to provide digital logical distribution, a third set of metal layers used to provide power distribution and a fourth set of metal layers used to provide RF signal distribution. The PWB comprises at least one transmit/receive (T/R) channel used in an AESA.

Abstract: A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components.

Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.

Abstract: A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components.

Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.

Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.

Abstract: A radiator includes a waveguide having an aperture and a patch antenna disposed in the aperture. In one embodiment, an antenna includes an array of waveguide antenna elements, each element having a cavity, and an array of patch antenna elements including an upper patch element and a lower patch element disposed in the cavity.

Abstract: A radiator includes a waveguide having an aperture and a patch antenna disposed in the aperture. In one embodiment, an antenna includes an array of waveguide antenna elements, each element having a cavity, and an array of patch antenna elements including an upper patch element and a lower patch element disposed in the cavity.