Abstract: A process (20) and design tool (62) are presented for the accurate prediction of design parameters (42) for components (38) of an integrated circuit (22) during the early stages of the design of that integrated circuit (22). These predicted design parameters (42) include pin count parameters (50), propagation delay parameters (52), layout area parameters (54), dynamic power parameters (56), static power parameters (58), and total power parameters (60). With these parameters, the designer interactively modifies the design prior to the layout and prototyping of the integrated circuit (22). The dynamic power parameters (56) and total power parameters (60) may be repetitively predicted with differing input items to establish a power usage pattern for the integrated circuit (22).

Abstract: A process (20) and design tool (62) are presented for the accurate prediction of design parameters (42) for components (38) of an integrated circuit (22) during the early stages of the design of that integrated circuit (22). These predicted design parameters (42) include pin count parameters (50), propagation delay parameters (52), layout area parameters (54), dynamic power parameters (56), static power parameters (58), and total power parameters (60). With these parameters, the designer interactively modifies the design prior to the layout and prototyping of the integrated circuit (22). The dynamic power parameters (56) and total power parameters (60) may be repetitively predicted with differing input items to establish a power usage pattern for the integrated circuit (22).

Abstract: A process (20) is presented for determining the total routine energy (78) consumed by a processor (22) during the execution of a code routine (36). This total routine energy (78) is computed by determining the operation energy (76) consumed in the execution of each operating instruction (38) within the code routine (36). The operation energy (76) for each operating instruction (38) is computed by determining the average operation power (74) consumed during the execution of the operating instruction (38). The average operation power (74) for each operating instruction (38) is determined by determining an instruction power (90) and a summed-action power (92) for that operating instruction (38). The summed-action power (92) is the sum of action powers (96) computed through the use of an action formula (100) for each internal action (88) performed by the processor (22) in response to the operating instruction (38).

Abstract: A messaging receiver (400) and corresponding system (100b) and method adaptable to a plurality of modulation formats including; a processor (401) having flexible resources (404), preferably software based, for receiving a signal to provide a modulation identifier, and a controller (403), coupled to the processor, for deploying the flexible resources responsive to the modulation identifier. Alternatively the messaging receiver includes a buffer (412) for storing a signal having a modulation format, and the processor processes the signal in accordance with the plurality of modulation formats so as to differentiate the modulation format, and the controller deploys the flexible resources responsive to the modulation format.

Abstract: Interference removal in spread spectrum signals, comprises the steps at a spread spectrum transmitter (10) of spreading information across a predetermined spectrum by phase modulating a repeating noise sequence (18), providing a spread spectrum signal and transmitting the spread spectrum signal. The method further comprises the steps at a receiver of receiving the spread spectrum signal along with interference (41) multiplying (42) the spread spectrum signal along with interference by a window function (44) providing a multiplied spread spectrum signal. The information is recovered by despreading the multiplied (48) spread spectrum signal using a reciprocal (50) of the spectrum of the repeating noise sequence to obtain a data spectrum with interference and subsequently normalize (52) to obtain a clean data spectrum. Alternatively the information can be recovered by substituting a corrupted magnitude spectrum with a prestored PN sequence magnitude spectrum (70) as shown by receiver (60).

Abstract: An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.

Abstract: A method and apparatus for connecting signal leads to an integrated circuit transmits a distribution signal on a lead. A substrate is provided with leads interconnecting a number of bonding pads. The integrated circuit has a corresponding number of bonding pads. An insulation layer is interposed between the integrated circuit and the substrate except for the bonding pads. The distribution lead is connected to the bonding pads on the substrate. The bonding pads of the substrate and the bonding pads of integrated circuit are interconnected. With this approach, signals may be distributed radially from a central point to equidistant circuits instead of sequentially or serially through a number of circuits.

Abstract: A complex arithmetic processor and method includes a host interface for distributing data, a left memory and a right memory each coupled to the host interface, and a Z memory coupled to the host interface. The left memory and the right memory store the data and the Z memory stores Z memory data. A right/left switch is coupled to the left memory and to the right memory and makes left memory a data source and a right memory a data destination in a first setting, and makes the right memory the data source and the left memory the data destination in a second setting. An arithmetic engine is coupled to the host interface, to the Z memory, and to the left and right memories. The arithmetic engine uses the data and the Z memory data to perform an operation on the data to produce a result.

Abstract: A special functions arithmetic logic unit (ALU) method and apparatus includes an ALU register, an ALU register value processor coupled to the ALU register for receiving and processing ALU register values to produce output data, and a normalizer. The normalizer receives and processes complex memory values to produce normalized output data independently of the output data from the ALU register value processor. The ALU register value processor includes a parser, combiner, polynomial divider, magnitude estimator, and a Hamming distance determiner. The normalizer includes an exponent determiner and first and second scalers for producing normalized X and Y data of the normalized output data.

Abstract: Method and arrangement for an airborne radar system particularly adapted to detect large metal targets that are concealed from the air by camouflage or natural foliage. The arrangement includes an antenna that transmits a continuous wave electromagnetic signal having a selectable frequency that preferably has a wave length generally twice the length of an anticipated target and which is carried by a flying vehicle. The frequency of the transmitted signal is chosen to provide maximum penetration of the camouflage or natural foliage and maximum re-radiation from a metal target. Receivers connected to an in-line receiving antenna and to a crossed receiving antenna carried by a flying vehicle detect the radiation that is reflected from the terrain and a target with the same polarization as that transmitted. The co-linear antenna and receiver respond to the reflected radiation while the cross-polarized antenna does not detect this reflected radiation.

Abstract: A bistatic VHF Doppler radar is utilized to detect and track one or more intruders crossing a large annular ring surveilance zone surrounding a central high security installation. A central omni-directional transmitter radiates the surveillance zone with a continuous wave (CW) signal. Predetermined ones of a plurality of receiver antennas circumferentially spaced around the surveillance zone receive a portion of the signal which is reflected by an intruder crossing the surveillance zone and a portion of the signal which is directly radiated from the transmitter antenna. The reflected signal portion may be received by antenna arrays each of which is controlled to form a null in its pattern toward the transmitter antenna to overcome direct signal overload. The direct signal portion may be received by stub antennas. Each antenna array and each stub antenna is connected to a separate channel of a dual channel receiver.

Abstract: A bistatic VHF Doppler radar is utilized to detect and track one or more intruders crossing a large annular ring surveilance zone surrounding a central high security installation. A central omni-directional transmitter radiates the surveillance zone with a continuous wave (CW) signal. Predetermined ones of a plurality of receiver antennas circumferentially spaced around the surveillance zone receive a portion of the signal which is reflected by an intruder crossing the surveillance zone and a portion of the signal which is directly radiated from the transmitter antenna. The reflected signal portion may be received by antenna arrays each of which is controlled to form a null in its pattern toward the transmitter antenna to overcome direct signal overload. The direct signal portion may be received by stub antennas. Each antenna array and each stub antenna is connected to a separate channel of a dual channel receiver.

Abstract: A control system for the automatic adjustment of controlling elements. The ystem includes a pulse controlled servo follow-up circuit, a signal generating circuit, a sensing circuit, a system controller and a switching circuit. The system controller is either a special or small general purpose digital device which transmits a control signal to the switching circuit in response to the output of the sensing circuit. The switching circuit provides either of two variable time duration pulse control signals to the pulse-controlled follow-up circuit. One control signal will cause the follow-up circuit to provide a positive control and the other control signal will cause negative control. The amount of positive or negative control is determined by the time duration of the pulse. The signal generating device will be controlled by the output of the follow-up circuit and the sensing circuit will measure the condition of the signal generating circuit.