Abstract: A sequencing column select circuit for a random access memory includes a decoder that decodes a column address to produce an output word having one bit asserted. The decoder transmits its output word through a first set of gates controlled by a STREAM signal to a recirculating shift register and to an output driver circuit. The shift register also supplies an output word to the output driver circuit through a second set of gates controlled by a !SHIFT signal. In response to an input word from either the shift register or the column decoder, the driver circuit produces output signals selecting memory cell columns for read or write access. When the STREAM signal is on and the !SHIFT signal is off, the decoder output word controls column selection in accordance with the column address. When the STREAM signal is off, the shift register bit shifts the driver circuit input in response to each occurrence of the !SHIFT signal so that a next column of the array is selected.