Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.

Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.

Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.

Abstract: An integrated circuit chip controls a bus and terminates at least one differential data line of the bus wherein the at least one differential data line includes a first bus line of the bus and a second bus line of the bus. The integrated circuit chip includes a package and a substrate. The package includes terminals that are configured to couple the package to the bus. A first terminal is configured to couple the package to the first bus line, and a second terminal is configured to couple the package to the second bus line. The substrate is supported by the package. Furthermore, the substrate includes a bus controller circuit coupled to the terminals and a terminating circuit coupled to the first terminal and the second terminal. The bus controller circuit is configured to control transfer of data on the bus, and the terminating circuit is configured to substantially match a characteristic impedance of the at least one differential data line.

Abstract: A method and apparatus is disclosed for terminating a SCSI bus having a SCSI port, with the SCSI port having a first set of I/O terminals associated only with wide SCSI buses and a second set of I/O terminals associated with both wide SCSI buses and narrow SCSI buses. The method includes the steps of determining if a first reference signal is present on one terminal of the first set of I/O terminals; determining if a second reference signal is present on one terminal of the second set of I/O terminals; and terminating each terminal of the first set of I/O terminals while not terminating any terminals of the second set of I/O terminals (1) if the first reference signal is not detected in the first reference signal determining step, and (2) if the second reference signal is detected in the second reference signal determining step.