Abstract: A system for determining the presence or absence of data on one or more data lines including a flip-flop for each data line with the output of each flip-flop connected to a NAND gate. The NAND gate is connected through an OR gate to two output flip-flops in series. The logic of the system is such that the output of the second of the two output flip-flops provides a signal level which is high or low depending on whether data is present on all of the data lines or one or more lines has no data.

Abstract: A frame detection circuit for SONET which operates in both the OC-3 and OC-12 modes. The frame detection circuit operates by examining the incoming data bit stream, detecting A1 and A2 bytes, and counting three consecutive A1 bytes immediately followed by three consecutive A2 bytes. Since the counters recycle upon reaching a three count, the circuit works for both the OC-3 and OC-12 modes.

Abstract: In a data transmission system, apparatus for converting a subrate binary data stream into a binary signal at the line transmission rate comprises means for periodically accepting a date byte from the subrate data stream and; means for expanding the data byte by one additional bit by adding a control bit in the first bit position of the accepting means. The apparatus additionally comprises means for recirculating the expanded data byte through the accepting means a predetermined number of times and means for serially reading out bits of the expanded data byte at the line transmission rate.

Abstract: A data rate converter for use in telecommunications inserts supervisory bits into a data stream to increase the data rate, in one application, from 56 kbps to a standard 64 kbps. A standard 64 kbps PCM telephone channel uses 8-bit words for transmission, whereas 56 kbps occupies only 7 bits of an 8 bit word in such a telephone channel. Supervisory bits are inserted at the exact time when the data channel clock signal and the transmission line clock signal are in phase alignment.