Patents by Inventor John B. Riley
John B. Riley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11344328Abstract: In one instance, a medical device for harvesting epidermal tissue from a patient includes a first compartment that is mateable with a second, disposable compartment that goes against the skin. The first compartment has a floor that is formed, at least in part, by a first printed circuit board. The ceiling of the second, disposable compartment is formed at least in part by a second printed circuit board that electrically couples with the first printed circuit board when in a mated position. Suction is delivered to the second compartment to pull skin through apertures on the floor of the second compartment to form blisters that are harvested to obtain epidermal tissue. The first compartment remains uncontaminated in use and the second compartment is disposable. Other features are presented; some of which include a thermal sensor in the second compartment for temperature control, clear side walls, and a distributed heating element.Type: GrantFiled: September 19, 2019Date of Patent: May 31, 2022Assignee: Tara Medical Devices, LLCInventors: John B. Riley, III, Max Alan Probasco
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Publication number: 20210085355Abstract: In one instance, a medical device for harvesting epidermal tissue from a patient includes a first compartment that is mateable with a second, disposable compartment that goes against the skin. The first compartment has a floor that is formed, at least in part, by a first printed circuit board. The ceiling of the second, disposable compartment is formed at least in part by a second printed circuit board that electrically couples with the first printed circuit board when in a mated position. Suction is delivered to the second compartment to pull skin through apertures on the floor of the second compartment to form blisters that are harvested to obtain epidermal tissue. The first compartment remains uncontaminated in use and the second compartment is disposable. Other features are presented; some of which include a thermal sensor in the second compartment for temperature control, clear side walls, and a distributed heating element.Type: ApplicationFiled: September 19, 2019Publication date: March 25, 2021Inventors: John B. Riley, III, Max Alan Probasco
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Patent number: 8329581Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.Type: GrantFiled: July 14, 2011Date of Patent: December 11, 2012Assignee: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
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Publication number: 20110269272Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.Type: ApplicationFiled: July 14, 2011Publication date: November 3, 2011Applicant: TESSERA, INC.Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
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Patent number: 7999397Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.Type: GrantFiled: May 28, 2010Date of Patent: August 16, 2011Assignee: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
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Patent number: 7935569Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.Type: GrantFiled: October 23, 2007Date of Patent: May 3, 2011Assignee: Tessera, Inc.Inventors: Kyong-Mo Bang, David Gibson, Young-Gon Kim, John B. Riley, III
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Publication number: 20100258956Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.Type: ApplicationFiled: May 28, 2010Publication date: October 14, 2010Applicant: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
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Patent number: 7745943Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.Type: GrantFiled: May 3, 2007Date of Patent: June 29, 2010Assignee: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
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Patent number: 7453157Abstract: A microelectronic package includes a microelectronic element having faces, contacts and an outer perimeter, and a flexible substrate overlying and spaced from a first face of the microelectronic element, an outer region of the flexible substrate extending beyond the outer perimeter of the microelectronic element. The package includes a plurality of etched conductive posts exposed at a surface of the flexible substrate and being electrically interconnected with the microelectronic element, wherein at least one of the conductive posts is disposed in the outer region of the flexible substrate, and a compliant layer disposed between the first face of the microelectronic element and the flexible substrate, wherein the compliant layer overlies the at least one of the conductive posts that is disposed in the outer region of the flexible substrate.Type: GrantFiled: May 27, 2005Date of Patent: November 18, 2008Assignee: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
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Patent number: 7294928Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.Type: GrantFiled: September 5, 2003Date of Patent: November 13, 2007Assignee: Tessera, Inc.Inventors: Kyong-Mo Bang, David Gibson, Young-Gon Kim, John B. Riley
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Patent number: 7149095Abstract: A stacked microelectronic assembly includes a plurality of microelectronic subassemblies. Each subassembly includes a substrate having at least one site, a plurality of first contacts and a plurality of second contacts. Each subassembly also has at least one microelectronic element assembled to the at least one attachment site and electrically connected to at least some of the first and second contacts. The substrate is folded so that the first contacts are accessible at a bottom of a subassembly and the second contacts are accessible at a top of a subassembly. The plurality of subassemblies are stacked one on top of another in a generally vertical configuration. The substrate of at least one of the subassemblies has a plurality of attachment sites and a plurality of microelectronic elements assembled to the attachment sites. The substrate is folded so that at least some of the plurality of microelectronic elements are disposed alongside one another.Type: GrantFiled: October 28, 2002Date of Patent: December 12, 2006Assignee: Tessera, Inc.Inventors: Michael Warner, Philip Damberg, John B. Riley, David Gibson, Young-Gon Kim, Belgacem Haba, Vernon Solberg
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Patent number: 6885106Abstract: A stacked microelectronic assembly includes a dielectric element and a first and second microelectronic element stacked one atop the other with the first microelectronic element disposed between the second microelectronic element and the dielectric. The dielectric element has opposed first and second surfaces with conductive features exposed at the first surface and terminals exposed on the second surface. Preferably, the contact-bearing face of the first microelectronic element confronts the first surface of the dielectric with at least some of the conductive features being movable with respect to the contacts or terminals. By providing such movable features, joining units have heights of about 300 microns or less may be joined to the terminals thereby reducing the overall height of the microelectronic assembly to 1.2 mm and less.Type: GrantFiled: January 11, 2002Date of Patent: April 26, 2005Assignee: Tessera, Inc.Inventors: Philip Damberg, Craig S. Mitchell, John B. Riley, Michael Warner, Joseph Fjelstad
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Publication number: 20040145054Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.Type: ApplicationFiled: September 5, 2003Publication date: July 29, 2004Applicant: Tessera, Inc.Inventors: Kyong-Mo Bang, David Gibson, Young-Gon Kim, John B. Riley
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Publication number: 20030168725Abstract: A stacked microelectronic assembly comprises a plurality of subassemblies including folded substrates and at least one microelectronic element. The subassemblies are stacked substantially vertically.Type: ApplicationFiled: October 28, 2002Publication date: September 11, 2003Applicant: Tessera, Inc.Inventors: Michael Warner, Philip Damberg, John B. Riley, David Gibson, Young-Gon Kim, Belgacem Haba, Vernon Solberg
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Publication number: 20030048624Abstract: A microelectronic assembly has a first microelectronic element, a second microelectronic element, and a structure which projects downwardly from the second microelectronic element and at least partially encompassing the first microelectronic element. The structure is at least partially flexible. A method of making a microelectronic assembly with a structure that is at least partially flexible is also disclosed.Type: ApplicationFiled: August 21, 2002Publication date: March 13, 2003Applicant: Tessera, Inc.Inventors: Philip Damberg, Craig S. Mitchell, John B. Riley, Michael Warner
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Patent number: 5856911Abstract: An integrated circuit package has a top die attach area and a bottom heat spreader thermally coupled to the die for conducting heat generated by the die through a thermal interface in the main circuit board to a heat sink or heat pipe mounted underneath the main circuit board. The preferred thermal interface is a thin, thermally conductive slug mounted through an opening formed in the main circuit board. The heat spreader spans the bottom surface of the integrated circuit package substantially parallel to the main circuit board and preferably extends substantially to the inner periphery of the pin arrangement which preferably, although not exclusively, is in a ball grid array. The opening formed in the main circuit board through which the thin, thermally conductive slug is fitted, is preferably substantially flush with the bottom surface of the main circuit board and juxtaposed against the heat spreader.Type: GrantFiled: November 12, 1996Date of Patent: January 5, 1999Assignee: National Semiconductor CorporationInventor: John B. Riley