Abstract: A thermoelectric conversion module includes an insulative substrate, a plurality of thermoelectric conversion material films disposed with a gap therebetween on a first surface of the insulative substrate and made of any one of an n-type thermoelectric conversion material and a p-type thermoelectric conversion material, a first electrode and a second electrode, formed away from each other on each of the thermoelectric conversion material films, a first thermal conduction member disposed on a side of the first surface of the insulative substrate and including a protruding portion in contact with the first, electrodes or the insulative substrate between the first electrodes, and a second thermal conduction member disposed on a side of a second surface of the insulative substrate and including a protruding portion in contact with the second surface of the insulative substrate at an area coinciding with the second electrodes.

Abstract: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.

Abstract: A superconducting tunable filter comprises a dielectric base plate; a patch-shaped resonator pattern formed of a superconducting material on the dielectric base plate; a top dielectric locally placed on the superconducting resonator pattern at a prescribed position and made of a material with an electric-field dependent permittivity; a conducting pattern formed on a top face of the top dielectric; and a bias voltage supply configured to apply a bias voltage between the conducting pattern and the superconducting resonator pattern.

Abstract: The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor electrode 18 formed over the capacitor dielectric film 16; leading-out electrodes 26a, 26b lead from the first capacitor electrode 14 or the second capacitor electrode 18 and formed of a conducting barrier film which prevents the diffusion of hydrogen or water; and outside connection electrodes 34a, 34b for connecting to outside and connected to the leading-out electrodes 26a, 26b.

Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.

Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).

Abstract: The present invention comprises the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.

Abstract: A probe card including probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.

Abstract: In one aspect of the invention, in a thin layer capacitor element comprising a capacitor having a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.

Abstract: To provide a thin-film capacitor and a semiconductor device capable of preventing a reduction in the dielectric constant due to a residual tensile stress in a ferroelectric layer in a thin-film capacitor using the ferroelectric substance, and increasing the dielectric constant and increasing an electric capacity. In a thin-film capacitor 10 having a lower electrode 2, a ferroelectric layer 3, and an upper electrode 4 on a substrate 1, the thin-film capacitor 10 has the upper electrode 4 that adds a compressive stress to the ferroelectric layer 3, and a residual compressive stress in the upper electrode 4 is within a range from 108 to 6×1011 dyne/cm2.

Abstract: A capacitive element includes a base member 10, an underlying insulating film 11 formed on the base member 10, a capacitor Q constructed by forming a lower electrode 13, a capacitor dielectric film 14, and an upper electrode 15 sequentially on the underlying insulating film 11, a lower protection insulating film 16a formed on the upper electrode 15 to cover at least a part of the capacitor Q, and an upper protection insulating film 16b formed on the lower protection insulating film 16a and having a wider energy band gap than the lower protection insulating film 16a.

Abstract: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.

Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.

Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 so that the ten-point height of irregularities of the surface of the resin layer 10 is 0.5-5 ?m; the step of forming a seed layer 36 on the resin layer 10; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.

Abstract: A capacitive element which includes: a silicon substrate (base material) 1; a base insulating film 2 formed on the silicon substrate 1; and a capacitor Q constituted by forming a bottom electrode 4a, a capacitor dielectric film 5a and a top electrode 6a on the base insulating film 2. The capacitive element is characterized in that the capacitor dielectric film 5a is composed of a material with the formula (Ba1?y,Sry)mYpTiQO3+?, where 0<p/(p+m+Q)?0.015, ?0.5<?<0.5.

Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.

Abstract: An SiO2 layer (3), a Ti layer (4), a Pt layer (5), a PLZT layer (6) and an IrO2 layer (7) are formed sequentially on an Si substrate (2). The IrO2 layer (7) functioning as a top electrode has a thickness of about 100 nm. Since the IrO2 layer (7) has conductivity lower than that of Pt or the like conventionally used as a top electrode and a skin depth deeper than that of Pt or the like, sufficient sensitivity can be attained by a thickness of about 100 nm.

Abstract: After a step of fabricating a MOS transistor (14) on a semiconductor substrate (11) and further steps up to bury a W plug (24), an Ir film (25a), an IrOy film (25b), a PZT film (26), and an IrOx film (27) are formed sequentially over the entire surface. The composition of the PZT film (26) is such that the content of Pb exceeds that of Zr and that of Ti. After processing the Ir film (25a), the IrOy film (25b), the PZT film (26) and the IrOx film (27), annealing is effected to remedy the damage to the PZT film (26) that is caused when the IrOx film (27) is formed and to diffuse Ir in the IrOx film (27) into the PZT film (26). As a result, the Ir diffused into the PZT film (26) concentrates at an interface between the IrOx film (27) and the PZT film (26) and at grain boundaries in the PZT film (26), and the Ir concentrations at the interface and boundaries are higher than those in the grains.

Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed an a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).