Abstract: A marine hydraulic system and method of use for reducing cyclic loading of the pump(s) and motor(s) and an amount of accumulator storage required in a hydraulic system. A closed loop logic controller comprising at least one control algorithm for each pump/motor pair utilized in a single hydraulic system is utilized to reduce load fluctuations on the motors, allow the use of common pressure compensated, variable displacement (VDH) pumps, reduce the number and/or volume of system accumulators and equalize wear throughout the system.

Abstract: The object of the invention is to provide a system that will allow multiple participants in remote locations to participate in a board game. The disclosure presented herein relates to a remote gameplay platform. Multiple instances of the platform may be combined to form a platform network, or a platform may be combined with virtual instances of the platform that would allow remote users to physically manipulate the board from remote locations.

Abstract: A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set. Also provided is a design structure embodied in a machine readable medium used in a design process.

Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.

Abstract: Dynamic random access memory (DRAM) sensing is accomplished by using capacitive mismatch between a bit line without a cell and a corresponding bit line with a cell to determine if a selected capacitor holds a one or a zero. Isolators on the bit lines are used to create the mismatch. In this manner, reference cells and bit-line twisting are eliminated, while maintaining rail pre-charge at VDD or ground. Utilizing short bit-lines, ‘Zero’ (for GND pre-charge) can be sensed by means of inherent capacitive mis-match. The zero will hold the bit-line at GND, the bit-line without a cell (or with fewer cells) will have less capacitance and rise faster than the bit-line with the cell due to capacitive mis-match. For sensing a ‘one’, the bit-line will have enough signal to overcome the capacitive mis-match.

Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.

Abstract: A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

Abstract: A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.

Abstract: A bitline structure for a memory array includes a first pair of complementary bitlines and a second pair of complementary bitlines. Both the first and second pair of complementary bitlines have a twist at a location corresponding to about ¼ of the total length of the bitline structure. The second pair of complementary bitlines further have a twist at a location corresponding to about ½ of the total length of the bitline structure, and both the first and second pair of complementary bitlines have a twist at a location corresponding to about ¾ the total length of the bitline structure.

Abstract: A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.

Abstract: A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

Abstract: A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.

Abstract: A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding plurality of data receiving storage elements receives the data transmitted from said transmitting storage elements. Encoding logic is used for encoding the transmitted data from the transmitting storage elements, wherein the encoded transmitted data is coupled to a plurality of data lines. The encoding logic is further configured so as to result in only one of the plurality of data lines being activated during a given data transmission cycle.

Abstract: A method and electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch and other logic components the eFuse circuit. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output generated by the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain depending on whether the next fuse is to be blown. Accordingly, rather than serially shifting through each fuse latch within the device, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

Abstract: The improved reference cell configurations having reduced pre-charge time are obtained by configurations where the reference cell pre-charge level is generated with a voltage regulator (or other power supply) and is directly written into each reference cell. The direct write reference cell configuration improves cycle time of operation when incorporated into sense amplifier and/or DRAM devices.