Abstract: Processors, systems, and methods for virtual address translation by a processor for a peripheral device are disclosed. In one embodiment, a processor includes a memory management unit and an interface. The memory management unit is to translate a first address to a second address. The first address is an address usable by software to access the virtual memory space of the processor. The second address is an address usable by the processor to access the physical memory space of the processor. The interface is to receive the first address from a peripheral device, to receive a request to translate the first address, and to transmit the second address to the peripheral device for the peripheral device to use to access the physical memory space of the processor.

Abstract: A bus bridging method, a bus bridge and a bus agent are described. In a bus agent provides to a bus bridge a read data request targeting a data source bridged by the bus bridge. The read data request includes a read address indicating a starting storage location of the requested data, and a read size indicator indicating the size of the requested data. The bus bridge, in response, facilitates provision of the requested data to the bus agent. The facilitation includes streaming buffered ones of the requested data to the bus agent through one or more successive streaming connections to the bus bridge by the bus agent.