Abstract: A delta-sigma modulator for an analog-to-digital converter device and method for reducing a quantization error resulting from differences between the periods of the delta-sigma quantizer clock and the counter clock by using a pulse-width modulator in which the timing of the rising edge of each pulse is controlled by a relatively low-frequency clock signal, and the trailing edge of each pulse is controlled by the input analog signal level. Accordingly, the device and method are particularly effective for measuring the duty cycle of a pulse train from a delta-sigma analog-to-digital converter device when it is undesirable to run the high-frequency clock signal between the pulse-width modulator and the counter, for example when significant physical separation between the delta-sigma modulator and the counter.

Abstract: A delta-sigma modulator for an analog-to-digital converter device and method for reducing a quantization error resulting from differences between the periods of the delta-sigma quantizer clock and the counter clock by using a pulse-width modulator in which the timing of the rising edge of each pulse is controlled by a relatively low-frequency clock signal, and the trailing edge of each pulse is controlled by the input analog signal level. Accordingly, the device and method are particularly effective for measuring the duty cycle of a pulse train from a delta-sigma analog-to-digital converter device when it is undesirable to run the high-frequency clock signal between the pulse-width modulator and the counter, for example when significant physical separation between the delta-sigma modulator and the counter.