Patents by Inventor John Bentley

John Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11098589
    Abstract: A hybrid elastomer/metal on metal motor for a helical gear device includes a rotor and stator comprising a hydraulic motor that produces work when a working fluid is pumped therethrough. The improvement involves the stator being, for part of its length, a conventional or even wall stator, using an elastomer to form a seal against the moving rotor. The stator's remaining length comprises a profiled rigid surface that forms a seal directly with the moving rotor. This gives the motor the high efficiency of the elastomer sealing against the rotor, and simultaneously provides a backup of the stator's rigid section allowing continued motor operation at reduced efficiency, if the elastomer part failed in service. The invention also includes combinations of a regular disk stack with a rubber lining, a rigid material disk stack (or unitized element) and a circular rigid sleeve which react to rotor sideloading while permitting proper rotor orbiting.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 24, 2021
    Assignee: Roper Pump Company
    Inventors: John Eugene Purcell, Tyson Bentley Anderson, Edmond Tate Coghlan
  • Publication number: 20210249352
    Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 12, 2021
    Inventors: STEVEN ROBERT SOSS, STEVEN JOHN BENTLEY, JULIEN FROUGIER
  • Publication number: 20190035566
    Abstract: A switch conversion apparatus including an interface device, a mounting plate configured to mount to a toggle switch and including at least one aperture for receiving a toggle arm of a toggle switch, and an actuator plate configured to slidably engage the mounting plate and including at least one aperture for receiving and engaging a toggle arm of a toggle switch when engaged by the interface device so as to transition the state of the switch. Other embodiments of a switch conversion apparatus include one or more mechanical, electrical, and/or pneumatic timers.
    Type: Application
    Filed: October 4, 2018
    Publication date: January 31, 2019
    Applicant: Effortless Systems, LLC
    Inventors: Michael S. Mahle, Mark P. Rau, Craig F. Hofmann, Craig Person, John F. Kasper, Daniel John Bentley, Scott D. Reiner, Christopher J. Lundgren
  • Patent number: 10141446
    Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki Niimi, Kwan-Yong Lim, Steven John Bentley, Daniel Chanemougame
  • Publication number: 20180061993
    Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.
    Type: Application
    Filed: October 25, 2017
    Publication date: March 1, 2018
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki NIIMI, Kwan-Yong LIM, Steven John BENTLEY, Daniel CHANEMOUGAME
  • Publication number: 20170358687
    Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki NIIMI, Kwan-Yong LIM, Steven John BENTLEY, Daniel CHANEMOUGAME
  • Patent number: 9842933
    Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 12, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki Niimi, Kwan-Yong Lim, Steven John Bentley, Daniel Chanemougame
  • Publication number: 20170278313
    Abstract: A device, method, and system may remotely monitor one or more subsystems in a terrestrial vehicle. In one embodiment, a method and system may schedule maintenance and order replacement parts after comparing the reported data with threshold data. In one embodiment, stake-holders, law enforcement entities, government agencies, and national security organizations may access the reported data. In one embodiment, a modular device may monitor vehicle subsystems, vehicle environmental data, a driver's heart beat, a driver's eye activity, a driver's head position, vehicle environmental data, and a driver's ID data.
    Type: Application
    Filed: March 22, 2016
    Publication date: September 28, 2017
    Inventors: Nermin Maslar, Awais Agha, John Bentley, Bob King, Norman D Dean
  • Patent number: 9615266
    Abstract: In one embodiment, a networking device comprises a first plurality of antenna means, a second plurality of antenna means, and means for controlling the first and second pluralities of antenna means to direct a communication towards a neighbor node of the device.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: April 4, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Christopher A. Cheadle, Steven Anthony Granzella, John A. Bentley
  • Patent number: 9564486
    Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 7, 2017
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION
    Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
  • Patent number: 9543215
    Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kwan-Yong Lim, Steven John Bentley, Chanro Park
  • Patent number: 9536793
    Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John H. Zhang, Kwan-Yong Lim, Steven John Bentley, Chanro Park
  • Publication number: 20160307807
    Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).
    Type: Application
    Filed: April 20, 2015
    Publication date: October 20, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kwan-Yong LIM, Steven John BENTLEY, Chanro PARK
  • Patent number: 9324790
    Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 26, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
  • Publication number: 20160035728
    Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 4, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Steven John Bentley, Murat Kerem Akarvardar, Jody Alan Fronheiser, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Toshiharu Nagumo
  • Publication number: 20150372080
    Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.
    Type: Application
    Filed: August 28, 2015
    Publication date: December 24, 2015
    Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
  • Patent number: D806760
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 2, 2018
    Assignee: Earth & Turf Products, LLC
    Inventor: John A. Bentley
  • Patent number: D899724
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: October 20, 2020
    Inventor: John A. Bentley
  • Patent number: D903965
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 1, 2020
    Assignee: Earth & Turf Products, LLC
    Inventor: John A. Bentley
  • Patent number: D920387
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 25, 2021
    Assignee: CONESTOGA MANUFACTURING, LLC
    Inventor: John A. Bentley