Abstract: Circuits, methods, and apparatus that reduce the power consumed by data transfers initiated by a USB host controller. Peripheral devices on a USB network are accessed with a reduced frequency in order to save power dissipated by a CPU and other circuits when reading data needed by the host controller. Instead of possibly accessing devices each frame, peripheral devices are accessed during some frames, and not accessed during others. A USB host controller may have two or more modes, such as a low power mode and a regular mode. In the low power mode, USB devices are accessed during fewer than all frames, in the regular mode, USB devices are possibly accessed each frame. Mode selection may depend on whether battery power is used.

Abstract: Circuits, methods, and apparatus that reduce the power consumed by transactions initiated by a number of USB host controllers. Peripheral devices on a number of USB networks are accessed in a coordinated manner in order to reduce power dissipated by a CPU and other circuits when reading data needed by the host controllers. The resulting memory reads are temporally clustered. This allows the CPU to process a greater number of requests each time it leaves a low-power state. As a result, the CPU may possibly remain in a sleep state for a longer period of time, thus saving power. This is accomplished at the host controller level by synchronizing the time frames used by each host controller in a system. The synchronizing signal may be one or more bits of a frame count provided by one host controller to a number of other frame controllers.

Abstract: Circuits, methods, and apparatus that increase utilization of available USB bandwidth, limit the amount of data accessed from memory, and provide for parallel requests for data from memory. An exemplary embodiment of the present invention caches a pointer for each transfer descriptor in a periodic and async schedule. Several transfer descriptors are also cached. Caching pointers reduces the time needed to organize the needed transfer descriptors to be transmitted. Caching several transfer descriptors eliminates the need to access the main memory each time they are needed. Also, if more transfer descriptors are needed beyond those in cache, memory requests for multiple transfer descriptors may be done in parallel since their pointers are available in cache.