Patents by Inventor John Bodenschatz

John Bodenschatz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital phase locked loop for regenerating the clock of an embedded signal
    Patent number: 7636409
    Abstract: The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: December 22, 2009
    Assignee: Broadcom Corporation
    Inventor: John Bodenschatz
  • DIGITAL PHASE LOCKED LOOP FOR REGENERATING THE CLOCK OF AN EMBEDDED SIGNAL
    Publication number: 20070086552
    Abstract: The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.
    Type: Application
    Filed: November 8, 2006
    Publication date: April 19, 2007
    Inventor: John Bodenschatz
  • Digital phase locked loop for regenerating the clock of an embedded signal
    Patent number: 7161998
    Abstract: The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: January 9, 2007
    Assignee: Broadcom Corporation
    Inventor: John Bodenschatz
  • Digital phase locked loop for regenerating the clock of an embedded signal
    Publication number: 20020122515
    Abstract: The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.
    Type: Application
    Filed: July 26, 2001
    Publication date: September 5, 2002
    Inventor: John Bodenschatz