Abstract: A circuit for reducing a time to switch between the redundant clock signals applied to a phase lock loop. The circuit includes a phase frequency detector of the phase lock loop that detects a shift in the phase of a reference clock signal relative to the phase of a feedback clock signal. The circuit further includes a coarse tuning mechanism configured to delay the feedback clock signal until the feedback clock signal is aligned with a backup reference clock signal. Furthermore, the circuit includes a fine tuning mechanism configured to align the edge of the feedback clock signal with the edge of the backup reference clock signal, such as by utilizing a series of delay elements to delay the backup reference clock signal at different points in time and selecting the appropriate delayed backup reference clock signal whose edge is aligned with the edge of the feedback clock signal.

Abstract: An integrated circuit includes at least one on-chip power conductor network, also referred to as a power grid, configured to distribute electrical power to a plurality of electrical components on the integrated circuit. Voltage drop detection circuitry selects each of a plurality of tap points from the on-chip power conductor network and in response to a plurality of selected tap points, provides data representing a frequency corresponding to a voltage level of each of the selected plurality of tap points. The data is used in some implementations to detect a short circuit in the power grid and in other implementations is used to generate a voltage drop map that identifies the locations in the power grid where power drops are beyond a desired threshold.

Abstract: Embodiments of the present disclosure provide enhanced systems and methods for detecting output power-ground shorts in on-chip voltage regulators, such as used for phase-locked loop (PLL) circuits in integrated circuit (IC) chips. A disclosed regulator output power-ground short detector can detect both initial output power-ground shorts of the on-chip voltage regulator including initial high resistance output power-ground shorts, and output power-ground shorts that can occur in a user's environment and degrade over time for example, resulting from a degrading or failing output voltage regulator analog (VRA) capacitor. In an embodiment, the regulator output power-ground short detector detects predefined threshold voltage offsets of a degraded power-ground short over time, and transmits warning notifications that enable corrective actions, such as repair or replacement before failure of the PLL circuits.

Abstract: A pulse limiter circuit of a phase-locked loop (PLL) receives, from a phase frequency detector of the PLL, first second input pulses, where pulse widths of the first and second input pulses indicate whether a reference clock signal leads or lags a feedback clock signal. The pulse limiter circuit determines whether a pulse width of the first or second input pulse is greater than a selected duration indicative of transient phase jitter. Based on determining the pulse width of the first or second input pulse is greater than the selected duration, the pulse limiter circuit sets a pulse width of a first output pulse equal to a pulse width of a second output pulse width and outputs the first and second output pulses to a charge pump of the PLL, such that no phase adjustment to the feedback clock signal is made based on the first and second input pulses.

Abstract: A circuit for reducing a time to switch between the redundant clock signals applied to a phase lock loop. The circuit includes a phase frequency detector of the phase lock loop that detects a shift in the phase of a reference clock signal relative to the phase of a feedback clock signal. The circuit further includes a coarse tuning mechanism configured to delay the feedback clock signal until the feedback clock signal is aligned with a backup reference clock signal. Furthermore, the circuit includes a fine tuning mechanism configured to align the edge of the feedback clock signal with the edge of the backup reference clock signal, such as by utilizing a series of delay elements to delay the backup reference clock signal at different points in time and selecting the appropriate delayed backup reference clock signal whose edge is aligned with the edge of the feedback clock signal.

Abstract: A pulse limiter circuit of a phase-locked loop (PLL) receives, from a phase frequency detector of the PLL, first second input pulses, where pulse widths of the first and second input pulses indicate whether a reference clock signal leads or lags a feedback clock signal. The pulse limiter circuit determines whether a pulse width of the first or second input pulse is greater than a selected duration indicative of transient phase jitter. Based on determining the pulse width of the first or second input pulse is greater than the selected duration, the pulse limiter circuit sets a pulse width of a first output pulse equal to a pulse width of a second output pulse width and outputs the first and second output pulses to a charge pump of the PLL, such that no phase adjustment to the feedback clock signal is made based on the first and second input pulses.

Abstract: Embodiments of the present disclosure provide an enhanced phase-locked loop (PLL) circuit and an enhanced charge pump circuit used for various applications, including high-speed data clock generation for complex integrated circuit (IC) designs. The disclosed PLL circuit and charge pump circuit enable significant power and supply current reduction, improved circuit reliability; reduced self-heating and electro-migration risk, and enable use of lower power operational amplifiers with the operational amplifiers driving high impedance nodes.

Abstract: On-chip spread spectrum synchronization between spread spectrum sources is provided. A spread spectrum amplitude of a signal of a spread spectrum reference clock is obtained using one or more delay lines of one or more delay elements in a skitter circuit. A spread width of the spread spectrum amplitude of the signal is determined, using one or more sticky latches in the skitter circuit, based on one or more edges of the signal. A delay line of the one or more delay elements corresponding to a falling edge of the spread width of the signal is identified using combinational circuitry of the skitter circuit. A spread spectrum signal of a spread spectrum slave clock is synchronized with the signal of the spread spectrum reference clock based on the delay line.

Abstract: On-chip spread spectrum synchronization between spread spectrum sources is provided. A spread spectrum amplitude of a signal of a spread spectrum reference clock is obtained using one or more delay lines of one or more delay elements in a skitter circuit. A spread width of the spread spectrum amplitude of the signal is determined, using one or more sticky latches in the skitter circuit, based on one or more edges of the signal. A delay line of the one or more delay elements corresponding to a falling edge of the spread width of the signal is identified using combinational circuitry of the skitter circuit. A spread spectrum signal of a spread spectrum slave clock is synchronized with the signal of the spread spectrum reference clock based on the delay line.

Abstract: A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.

Abstract: A phase locked loop having a charge pump is described. The charge pump relies on close matching of FETs (Field Effect Transistor) electrical parameters to FETs in a current reference circuit. To achieve close matching of FET electrical performance, FEOL (Front End Of Line), comprising all FET shapes, of the current pump is identical in shapes and layout to the current reference circuit. BEOL (Back End Of Line) differs between the charge pump and the current reference circuit. The charge pump and the current reference circuit are arranged in a row. A shield circuit having FEOL shapes and layout identical to the current pump may be placed at each end of the row.

Abstract: A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

Abstract: A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

Abstract: Techniques for analysis of verification parameters and reduction of training data are provided. A plurality of test results is received, where each of the plurality of test results specifies a respective one or more parameters and a respective one or more events. A list of parameters used to stimulate computing logic is determined. Additionally, a plurality of relevant parameters is generated, corresponding to parameters in the list of parameters that have at least two distinct values specified in the plurality of test results. A plurality of training cases is generated based on the plurality of test results and the plurality of relevant parameters. Further, a neural network is generated for design verification of the computing logic based on the plurality of relevant parameters. The neural network is trained based on the plurality of training cases.

Abstract: Detecting distortion in spread spectrum signals, including: identifying, based on a reference clock signal, one or more edges in a spread spectrum clock signal; incrementing one or more counters corresponding to the one or more edges, the one or more counters included in a plurality of counters; providing each bit of a respective output of the plurality of counters to a respective OR gate of a plurality of OR gates; and outputting, based on an output of an OR gate of the plurality of OR gates corresponding to a selected bit, an indication of whether distortion exists in the spread spectrum clock signal.

Abstract: The invention relates to a method, a circuit, and an apparatus for detecting distortion in spread spectrum signals. An edge in a spread spectrum clock signal is identified based on a reference clock signal. The edge data is then provided to a set of counters which are incremented corresponding to an identified edge. Each bit of a respective output of the counters are provided to a respective OR gate of a set of OR gates. An OR gate from the set of OR gates corresponding to a selected bit then outputs an indication of whether distortion exists in the spread spectrum clock signal.

Abstract: Techniques for analysis of verification parameters and reduction of training data are provided. A plurality of test results is received, where each of the plurality of test results specifies a respective one or more parameters and a respective one or more events. A list of parameters used to stimulate computing logic is determined. Additionally, a plurality of relevant parameters is generated, corresponding to parameters in the list of parameters that have at least two distinct values specified in the plurality of test results. A plurality of training cases is generated based on the plurality of test results and the plurality of relevant parameters. Further, a neural network is generated for design verification of the computing logic based on the plurality of relevant parameters. The neural network is trained based on the plurality of training cases.

Abstract: Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.

Abstract: Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.

Abstract: An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.