Patents by Inventor John Borkenhagen
John Borkenhagen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11693446Abstract: On-chip spread spectrum synchronization between spread spectrum sources is provided. A spread spectrum amplitude of a signal of a spread spectrum reference clock is obtained using one or more delay lines of one or more delay elements in a skitter circuit. A spread width of the spread spectrum amplitude of the signal is determined, using one or more sticky latches in the skitter circuit, based on one or more edges of the signal. A delay line of the one or more delay elements corresponding to a falling edge of the spread width of the signal is identified using combinational circuitry of the skitter circuit. A spread spectrum signal of a spread spectrum slave clock is synchronized with the signal of the spread spectrum reference clock based on the delay line.Type: GrantFiled: October 20, 2021Date of Patent: July 4, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Borkenhagen, Christopher Steffen, Grant P. Kesselring
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Publication number: 20230121692Abstract: On-chip spread spectrum synchronization between spread spectrum sources is provided. A spread spectrum amplitude of a signal of a spread spectrum reference clock is obtained using one or more delay lines of one or more delay elements in a skitter circuit. A spread width of the spread spectrum amplitude of the signal is determined, using one or more sticky latches in the skitter circuit, based on one or more edges of the signal. A delay line of the one or more delay elements corresponding to a falling edge of the spread width of the signal is identified using combinational circuitry of the skitter circuit. A spread spectrum signal of a spread spectrum slave clock is synchronized with the signal of the spread spectrum reference clock based on the delay line.Type: ApplicationFiled: October 20, 2021Publication date: April 20, 2023Inventors: JOHN BORKENHAGEN, CHRISTOPHER STEFFEN, GRANT P. KESSELRING
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Patent number: 11558057Abstract: A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.Type: GrantFiled: November 4, 2021Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: John Borkenhagen, Grant P. Kesselring, James Strom, Christopher Steffen
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Patent number: 11527953Abstract: A phase locked loop having a charge pump is described. The charge pump relies on close matching of FETs (Field Effect Transistor) electrical parameters to FETs in a current reference circuit. To achieve close matching of FET electrical performance, FEOL (Front End Of Line), comprising all FET shapes, of the current pump is identical in shapes and layout to the current reference circuit. BEOL (Back End Of Line) differs between the charge pump and the current reference circuit. The charge pump and the current reference circuit are arranged in a row. A shield circuit having FEOL shapes and layout identical to the current pump may be placed at each end of the row.Type: GrantFiled: October 21, 2021Date of Patent: December 13, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Strom, John Borkenhagen, Ann Chen Wu, Erik Unterborn, Grant P. Kesselring
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Patent number: 11496094Abstract: A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.Type: GrantFiled: April 26, 2021Date of Patent: November 8, 2022Assignee: International Business Machines CorporationInventors: James Strom, Herschel Akiba Ainspan, Andrew D. Davies, John Borkenhagen
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Publication number: 20220345085Abstract: A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Inventors: James Strom, Herschel Akiba Ainspan, Andrew D. Davies, John Borkenhagen
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Patent number: 11341034Abstract: Techniques for analysis of verification parameters and reduction of training data are provided. A plurality of test results is received, where each of the plurality of test results specifies a respective one or more parameters and a respective one or more events. A list of parameters used to stimulate computing logic is determined. Additionally, a plurality of relevant parameters is generated, corresponding to parameters in the list of parameters that have at least two distinct values specified in the plurality of test results. A plurality of training cases is generated based on the plurality of test results and the plurality of relevant parameters. Further, a neural network is generated for design verification of the computing logic based on the plurality of relevant parameters. The neural network is trained based on the plurality of training cases.Type: GrantFiled: August 6, 2018Date of Patent: May 24, 2022Assignee: International Business Machines CorporationInventors: Chad Albertson, John Borkenhagen, Scott D. Frei, David G. Wheeler, Mark S. Fredrickson
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Publication number: 20210320686Abstract: Detecting distortion in spread spectrum signals, including: identifying, based on a reference clock signal, one or more edges in a spread spectrum clock signal; incrementing one or more counters corresponding to the one or more edges, the one or more counters included in a plurality of counters; providing each bit of a respective output of the plurality of counters to a respective OR gate of a plurality of OR gates; and outputting, based on an output of an OR gate of the plurality of OR gates corresponding to a selected bit, an indication of whether distortion exists in the spread spectrum clock signal.Type: ApplicationFiled: April 13, 2020Publication date: October 14, 2021Inventors: JOHN BORKENHAGEN, CHRISTOPHER STEFFEN, GRANT P. KESSELRING
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Patent number: 11146307Abstract: The invention relates to a method, a circuit, and an apparatus for detecting distortion in spread spectrum signals. An edge in a spread spectrum clock signal is identified based on a reference clock signal. The edge data is then provided to a set of counters which are incremented corresponding to an identified edge. Each bit of a respective output of the counters are provided to a respective OR gate of a set of OR gates. An OR gate from the set of OR gates corresponding to a selected bit then outputs an indication of whether distortion exists in the spread spectrum clock signal.Type: GrantFiled: April 13, 2020Date of Patent: October 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Borkenhagen, Christopher Steffen, Grant P. Kesselring
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Publication number: 20200042434Abstract: Techniques for analysis of verification parameters and reduction of training data are provided. A plurality of test results is received, where each of the plurality of test results specifies a respective one or more parameters and a respective one or more events. A list of parameters used to stimulate computing logic is determined. Additionally, a plurality of relevant parameters is generated, corresponding to parameters in the list of parameters that have at least two distinct values specified in the plurality of test results. A plurality of training cases is generated based on the plurality of test results and the plurality of relevant parameters. Further, a neural network is generated for design verification of the computing logic based on the plurality of relevant parameters. The neural network is trained based on the plurality of training cases.Type: ApplicationFiled: August 6, 2018Publication date: February 6, 2020Inventors: Chad ALBERTSON, John BORKENHAGEN, Scott D. FREI, David G. WHEELER, Mark S. FREDRICKSON
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Patent number: 10528399Abstract: Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.Type: GrantFiled: January 5, 2018Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Mark S. Fredrickson, John Borkenhagen, Michael A. Muston, Spencer K. Millican, John D. Irish
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Publication number: 20190213050Abstract: Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.Type: ApplicationFiled: January 5, 2018Publication date: July 11, 2019Inventors: Mark S. FREDRICKSON, John BORKENHAGEN, Michael A. MUSTON, Spencer K. MILLICAN, John D. IRISH
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Publication number: 20080114913Abstract: An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.Type: ApplicationFiled: January 23, 2008Publication date: May 15, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Borkenhagen, Benjamin Carter, Stephen Levesque
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Publication number: 20070189313Abstract: A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.Type: ApplicationFiled: April 26, 2007Publication date: August 16, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Bartley, John Borkenhagen, Robert Drehmel, James Marcella
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Publication number: 20070168762Abstract: A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.Type: ApplicationFiled: November 30, 2005Publication date: July 19, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Bartley, John Borkenhagen, William Hovis, Daniel Kolz
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Publication number: 20070168617Abstract: A computer system having patrol snoop sequencer that sequences through addresses of cache lines held in a higher level cache, making snoop reads using those addresses to a lower level cache. If a particular cache line held in the higher level cache is not held in the lower level cache, the particular cache line is identified as an eviction candidate in the higher level cache when a new cache line must be loaded into the higher level cache.Type: ApplicationFiled: January 19, 2006Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: John Borkenhagen, Brian Vanderpool
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Publication number: 20070083681Abstract: An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.Type: ApplicationFiled: October 7, 2005Publication date: April 12, 2007Applicant: International Business Machines CorporationInventors: Gerald Bartley, John Borkenhagen, William Hovis, Daniel Kolz
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Publication number: 20070083682Abstract: A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.Type: ApplicationFiled: October 7, 2005Publication date: April 12, 2007Applicant: International Business Machines CorporationInventors: Gerald Bartley, John Borkenhagen, William Hovis, Daniel Kolz
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Publication number: 20060268519Abstract: A method and structure are provided for implementing enhanced cooling of a plurality of memory devices. The memory structure includes a stack of platters. A sub-plurality of memory devices is mounted on each platter. At least one connector is provided with each platter for connecting to the sub-plurality of memory devices. A heat sink is associated with the stack of platters for cooling the plurality of memory devices.Type: ApplicationFiled: May 26, 2005Publication date: November 30, 2006Applicant: International Business Machines CorporationInventors: Gerald Bartley, John Borkenhagen, William Cochran, William Hovis, Paul Rudrud
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Publication number: 20060187739Abstract: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Applicant: International Business Machines CorporationInventors: John Borkenhagen, Sudhir Dhawan, Philip Hillier, Joseph Kirscht, Randolph Kolvick