Patents by Inventor John Bracchitta
John Bracchitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7323382Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: GrantFiled: February 16, 2007Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
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Publication number: 20070204447Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: ApplicationFiled: February 16, 2007Publication date: September 6, 2007Applicant: International Business Machines CorporationInventors: Kerry Bernstein, John Bracchitta, William Cote, Tak Ning, Wilbur Pricer
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Patent number: 7195971Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: GrantFiled: February 28, 2005Date of Patent: March 27, 2007Assignee: International Business Machines CorporationInventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
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Publication number: 20060235719Abstract: An intellectual property management facility for proactively creating, developing and managing an intellectual property portfolio includes: determining available resource capacity for an intellectual property activity in a tracking system; assigning technical attributes to the activity in the tracking system; apportioning resource capacity for the activity by technical attribute based on the value assigned to each of the technical attributes and based on available resource capacity; obtaining actual resource usage by technical attribute from the tracking system; and managing resource allocation for the intellectual property activity by determining the difference between the actual resource usage and the resource allocation by technical attribute.Type: ApplicationFiled: June 14, 2006Publication date: October 19, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Bracchitta, Patricia Marmillion, Bernadette Pierson, Henry Rickers, Howard Walter
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Publication number: 20050139959Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: ApplicationFiled: February 28, 2005Publication date: June 30, 2005Applicant: International Business Machines CorporationInventors: Kerry Bernstein, John Bracchitta, William Cote, Tak Ning, Wilbur Pricer
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Patent number: 6882015Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: GrantFiled: September 12, 2003Date of Patent: April 19, 2005Assignee: International Business Machines CorporationInventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
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Patent number: 6858889Abstract: A process for forming capacitors in a semiconductor device.Type: GrantFiled: June 8, 2001Date of Patent: February 22, 2005Assignee: International Business Machines CorporationInventors: James W. Adkisson, John A. Bracchitta, Jed H. Rankin, Anthony K. Stamper
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Publication number: 20040046230Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: ApplicationFiled: September 12, 2003Publication date: March 11, 2004Applicant: International Business Machines CorporationInventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
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Patent number: 6677637Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: GrantFiled: June 11, 1999Date of Patent: January 13, 2004Assignee: International Business Machines CorporationInventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
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Patent number: 6660596Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.Type: GrantFiled: July 2, 2002Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: James W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson, Jed H. Rankin
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Patent number: 6483156Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.Type: GrantFiled: March 16, 2000Date of Patent: November 19, 2002Assignee: International Business Machines CorporationInventors: James W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson, Jed H. Rankin
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Publication number: 20020153587Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.Type: ApplicationFiled: July 2, 2002Publication date: October 24, 2002Applicant: International Business Machines CorporationInventors: James W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson, Jed H. Rankin
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Patent number: 6420746Abstract: A semiconductor integrated circuit memory cell, including at least three transistors and a capacitor to form a DRAM. The memory cell is fabricated on a semiconductor substrate including impurity regions, and using two semiconductor films, with dielectric films between the semiconductor films. The capacitor contains two electrodes. A substrate impurity region forms one of the electrodes; the other electrode is a semiconductor film which connects the gate of one device to an impurity region of another. The method for manufacturing the above-described integrated circuit, which may be used for the manufacture of similar circuits, is also disclosed.Type: GrantFiled: October 29, 1998Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: John A. Bracchitta, Randy W. Mann, Jeffrey H. Oppold
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Publication number: 20020082890Abstract: An intellectual property management facility for proactively creating, developing and managing an intellectual property portfolio includes: determining available resource capacity for an intellectual property activity in a tracking system; assigning technical attributes to the activity in the tracking system; apportioning resource capacity for the activity by technical attribute based on the value assigned to each of the technical attributes and based on available resource capacity; obtaining actual resource usage by technical attribute from the tracking system; and managing resource allocation for the intellectual property activity by determining the difference between the actual resource usage and the resource allocation by technical attribute.Type: ApplicationFiled: December 22, 2000Publication date: June 27, 2002Inventors: John A. Bracchitta, Patricia M. Marmillion, Bernadette A. Pierson, Henry C. Rickers, Howard J. Walter
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Publication number: 20020081832Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.Type: ApplicationFiled: June 11, 1999Publication date: June 27, 2002Inventors: KERRY BERNSTEIN, JOHN A. BRACCHITTA, WILLIAM J. COTE, TAK H. NING, WILBUR D. PRICER
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Patent number: 6394638Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.Type: GrantFiled: April 28, 2000Date of Patent: May 28, 2002Assignee: International Business Machines CorporationInventors: Edward W. Sengle, Mark D. Jaffe, Daniel Nelson Maynard, Mark Alan Lavin, Eric Jeffrey White, John A. Bracchitta
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Patent number: 6373095Abstract: A field effect floating gate transistor forming an NVRAM cell is disclosed. A substrate having field isolation structures includes therebetween a doped region forming a channel connecting a source and drain. An oxide layer is disposed over said channel forming a tunneling oxide layer for the device. A layer of polysilicon extends over the oxide layer, to each of the isolation structures and then extends upwards forming a U-shaped pillar floating gate. A second oxide layer disposed within the interior of the U-shaped floating gate supports a control gate. A second layer of polysilicon formed over the second oxide layer forms a control gate, and is connected to a conductor which is common to a row of such cells within a memory. The control gate is coupled to the floating gate through the second oxide layer to the upwardly extending layer of the floating gate as well as over the portion of the floating gate extending over the channel.Type: GrantFiled: February 25, 1998Date of Patent: April 16, 2002Assignee: International Business Machines CorporationInventors: John A. Bracchitta, James S. Nakos
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Publication number: 20020030216Abstract: A process for forming capacitors in a semiconductor device.Type: ApplicationFiled: June 8, 2001Publication date: March 14, 2002Inventors: James W. Adkisson, John A. Bracchitta, Jed H. Rankin, Anthony K. Stamper
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Patent number: 6344381Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.Type: GrantFiled: May 1, 2000Date of Patent: February 5, 2002Assignee: International Business Machines CorporationInventors: John A. Bracchitta, Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman
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Patent number: 6339015Abstract: A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate.Type: GrantFiled: May 18, 2000Date of Patent: January 15, 2002Assignee: International Business Machines CorporationInventors: John A. Bracchitta, James S. Nakos