Abstract: A microcontroller has a central processing unit coupled with a control unit for controlling a transmission bus. The transmission bus has at least one data and one clock signal with recessive and dominant states. The system comprises a bus controller for controlling a data and a clock line, a stretch control unit coupled with the clock line of the bus receiving a stretch activation signal, and a delay unit for delaying the stretch activation signal until a transition from a recessive to a dominant state on the clock line takes place. The bus can be an I2C-bus.

Abstract: A current compensating bias generator generates a current which follows voltage. The current compensating bias generator has a bias generator circuit for generating a current. A current compensating circuit is coupled to the bias generator circuit for changing a value of the current as a voltage input to the current compensating bias generator is changed. A resistive ladder circuit is coupled to the current compensating circuit for setting a voltage level trip point for the current compensating circuit at which the current compensating circuit is used to change the value of the current.