Patents by Inventor John Briar

John Briar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170178193
    Abstract: A sponsored data system configured to operate with a wireless mobile device running an app that receives sponsored data from a content provider server is provided. The system includes an interface application configured to run on the wireless mobile device. The interface application is configured to determine availability of sponsored data. A cloud platform is configured to interface with the content provider server. The cloud platform is configured to generate a token with data usable to determine availability of sponsored data and transmit the token to the interface application. A portal is configured to create and store a package that identifies at least a portion of the data associated with the app as sponsored data.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 22, 2017
    Inventors: Shantigram Venkatesh Jagannath, Harjot Singh Saluja, Sharmistha Chatterjee, Robin Balyan, Mahender Reddy Korandla, Avi Chopra, Minyan Shi, John Briar, Apratim Ankur, Abhishek Kumar
  • Patent number: 7081668
    Abstract: An Integrated Circuit package structure includes an Integrated Circuit device having a electrical contact points to the device in the bottom surface. A heatsink has a flat bottom surface extending past the device by a first distance and contacting the top surface of the device. A substrate has a flat upper surface extending past the device by the first distance and having points of electrical contact to the device and a lower surface having points of electrical contact for further interconnect of the substrate to surrounding circuitry or components with the upper and lower surfaces extending beyond the bottom surface of the device. A molding compound is between the flat bottom surface of the heatsink and the flat upper surface of the substrate to fill only the first distance and is among the points of electrical contact to the device.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: July 25, 2006
    Assignee: St Assembly Test Services Pte.
    Inventor: John Briar
  • Patent number: 6828671
    Abstract: A new method is provided for the establishment of a low resistivity connection between a wire bonded IC chip that is mounted on a heatsink and the heatsink of the package. A copper trace connection is allocated for this purpose on the surface of the substrate layer to which the IC chip is connected. An opening is provided in the substrate layer of the package, this opening aligns with the copper trace that has been allocated for establishing a ground connection and penetrates the substrate layer down to the surface of the underlying heatsink. The opening is filled with a conductive epoxy or an equivalent low-resistivity material thereby establishing a direct electrical connection or short between the allocated copper trace and the underlying heatsink. By connecting the ground point of the IC chip to the allocated copper trace, a direct electrical low resistivity connection is made between the ground point of the IC chip and the heatsink into which the IC chip is mounted.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: December 7, 2004
    Assignee: ST Assembly Test Services PTE LTD
    Inventors: Weddie Aquien, John Briar, Setho Sing Fee
  • Patent number: 6770962
    Abstract: A substrate and method of encapsulating a substrate based electronic package using injection molding and a two piece mold is described. The substrate has a barrier material formed on a gating region of the substrate. The barrier material can be formed directly over circuit wiring traces formed on the substrate thereby avoiding restrictions on the location of circuit wiring traces. The barrier material and encapsulant are chosen such that the adhesive force between the barrier material and the encapsulant is greater than the adhesive force between the barrier material and the substrate. When the mold runner is broken away the barrier material is also peeled away without damage to the substrate or circuit wiring traces.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: August 3, 2004
    Assignee: St Assembly Test Services Ltd.
    Inventor: John Briar
  • Patent number: 6759752
    Abstract: A package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: July 6, 2004
    Assignee: St Assembly Test Services Ltd.
    Inventors: Raymundo M. Camenforte, John Briar
  • Patent number: 6750082
    Abstract: A method of assembling a package having an exposed die comprising the following steps. A die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: June 15, 2004
    Assignee: Advanpack Solutions Pte. Ltd.
    Inventors: John Briar, Roman Perez, Tan Kim Hwee
  • Publication number: 20040084688
    Abstract: A new method is provided to provide the underfill for flip-chip semiconductor devices. An IC chip is provided with solder bumps. The flip-chip is inserted into a cavity, the heatsink forms the top of the cavity, a IC substrate forms the bottom of the cavity. The cavity is filled with a molding compound. This molding compound is forced around and under the IC chip, surrounding the IC chip including the area below the IC chip.
    Type: Application
    Filed: October 24, 2003
    Publication date: May 6, 2004
    Inventor: John Briar
  • Publication number: 20040084508
    Abstract: A method and structure for controlling solder spread in a predefined/designed area during flip chip assembly build is disclosed. Using conventional processes used in the art blind holes or dimples are incorporated onto the lead frame which then act as containers or wells trapping the solder and thereby preventing it from spreading wider.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Applicant: Advanpack Solutions Pte. Ltd.
    Inventors: John Briar, Roman Perez, Kee Kwang Lau, Alex Chew
  • Publication number: 20040053445
    Abstract: A method of assembling a package having an exposed die comprising the following steps. A die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.
    Type: Application
    Filed: September 13, 2002
    Publication date: March 18, 2004
    Applicant: Advanpack Solutions Pte. Ltd.
    Inventors: John Briar, Roman Perez, Tan Kim Hwee
  • Patent number: 6660565
    Abstract: In accordance with the objectives of the invention a new method is provided to insert the underfill for flip-chip semiconductor devices. An IC chip is provided with solder bumps. The flip-chip is entered into an enclosed space, the heatsink forms the top of the enclosed space, the substrate forms the bottom of the enclosed space. The enclosed space is filled with a mold compound. This mold compound now surrounds the IC chip thereby including the area below the IC. The step of inserting the underfill as a separate processing step has thereby been eliminated.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: December 9, 2003
    Assignee: St Assembly Test Services Pte Ltd.
    Inventor: John Briar
  • Patent number: 6617525
    Abstract: A molded flexible circuit assembly and method of forming a molded flexible circuit assembly which use a molded stiffener, and do not require any additional type of stiffener, are described. A molded stiffener is formed on a flexible tape at the same time molded encapsulation units are formed to encapsulate circuit die which are attached to the flexible tape. The molded stiffeners provide adequate rigidity for processing of the molded flexible circuit assembly. When the stiffeners are no longer needed they are removed at the same time the mold runners are removed. No additional processing steps are required for either the formation or removal of the molded stiffeners.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: September 9, 2003
    Assignee: St. Assembly Test Services Ltd.
    Inventors: John Briar, Raymundo M. Camenforte
  • Publication number: 20030151148
    Abstract: A new package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.
    Type: Application
    Filed: February 20, 2003
    Publication date: August 14, 2003
    Applicant: ST ASSEMBLY TEST SERVICES PTE LTD
    Inventors: Raymundo M. Camenforte, John Briar
  • Publication number: 20030085462
    Abstract: A new method is provided for the establishment of a low resistivity connection between a wire bonded IC chip that is mounted on a heatsink and the heatsink of the package. A copper trace connection is allocated for this purpose on the surface of the substrate layer to which the IC chip is connected. An opening is provided in the substrate layer of the package, this opening aligns with the copper trace that has been allocated for establishing a ground connection and penetrates the substrate layer down to the surface of the underlying heatsink. The opening is filled with a conductive epoxy or an equivalent low-resistivity material thereby establishing a direct electrical connection or short between the allocated copper trace and the underlying heatsink. By connecting the ground point of the IC chip to the allocated copper trace, a direct electrical low resistivity connection is made between the ground point of the IC chip and the heatsink into which the IC chip is mounted.
    Type: Application
    Filed: December 19, 2002
    Publication date: May 8, 2003
    Applicant: ST Assembly Test Services, Ltd.
    Inventors: Weddie Aquien, John Briar, Setho Sing Fee
  • Patent number: 6544812
    Abstract: A package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: April 8, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Raymundo M. Camenforte, John Briar
  • Patent number: 6543127
    Abstract: In accordance with the objectives of the invention a new method and apparatus is provide for assuring contact balls coplanarity. The process and apparatus for coplanarity inspection is integrated with the current processing step of BGA device singulation and pick-and-place, thereby eliminating the need for a separate processing step that is typically required for the coplanarity inspection.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: April 8, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Antonio B. Dimaano, Jr., Weddie Pacio Aquien, John Briar
  • Patent number: 6537857
    Abstract: A new method is provided for the establishment of a low resistivity connection between a wire bonded IC chip that is mounted on a heatsink and the heatsink of the package. A copper trace connection is allocated for this purpose on the surface of the substrate layer to which the IC chip is connected. An opening is provided in the substrate layer of the package, this opening aligns with the copper trace that has been allocated for establishing a ground connection and penetrates the substrate layer down to the surface of the underlying heatsink. The opening is filled with a conductive epoxy or an equivalent low-resistivity material thereby establishing a direct electrical connection or short between the allocated copper trace and the underlying heatsink. By connecting the ground point of the IC chip to the allocated copper trace, a direct electrical low resistivity connection is made between the ground point of the IC chip and the heatsink into which the IC chip is mounted.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: March 25, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Weddie Aquien, John Briar, Setho Sing Fee
  • Patent number: 6479903
    Abstract: A new method is provided for the conduction of heat between a flip-chip and the motherboard and heatsink onto which the flip-chip is mounted. In a flip-chip package of the invention the heatsink is in direct contact with the flex circuit, the contact balls of the flip chip make contact with the flex circuit. The flip-chip is attached and reflow is performed thereby attaching the contact balls to the flex circuit. The flip chip is encased in a molding compound in a one step process procedure that is in accordance with assigned to a common assignee. The flip-chip is now placed on the motherboard with the contact balls and the underfill facing upwards. The underfill provides direct contact between the flip-chip and the flex circuit/heatsink. This direct contact significantly increases the heat flow between the flip-chip and the heatsink.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: November 12, 2002
    Assignee: St Assembly Test Services Ltd.
    Inventor: John Briar
  • Publication number: 20020163064
    Abstract: A new method is provided for the establishment of a low resistivity connection between a wire bonded IC chip that is mounted on a heatsink and the heatsink of the package. A copper trace connection is allocated for this purpose on the surface of the substrate layer to which the IC chip is connected. An opening is provided in the substrate layer of the package, this opening aligns with the copper trace that has been allocated for establishing a ground connection and penetrates the substrate layer down to the surface of the underlying heatsink. The opening is filled with a conductive epoxy or an equivalent low-resistivity material thereby establishing a direct electrical connection or short between the allocated copper trace and the underlying heatsink. By connecting the ground point of the IC chip to the allocated copper trace, a direct electrical low resistivity connection is made between the ground point of the IC chip and the heatsink into which the IC chip is mounted.
    Type: Application
    Filed: May 7, 2001
    Publication date: November 7, 2002
    Applicant: St Assembly Test Services Pte Ltd
    Inventors: Weddie Aquien, John Briar, Setho Sing Fee
  • Patent number: 6432742
    Abstract: A method of fabricating a die-up laminated PBGA package, including the following steps. A mold chase for a PBGA package is provided. The mold chase has an open side with and exposed bottom wall and side walls, and a bottom side. The mold chase is positioned open side up. A heat spreader is dropped into the mold chase open side. The heat spreader has a lower protruding section, and lateral peripheral flanges with gaps therebetween. The protruding section contacts a portion of the bottom wall of the mold chase and the flanges contact a portion of the exposed side walls of the mold chase to thereby secure the heat spreader within the mold chase. A substrate, having a die affixed thereto in a die down position, is fixedly placed over the mold chase. The die being positioned within the space above the protruding section of the heat spreader.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: August 13, 2002
    Assignee: St Assembly Test Services Pte Ltd.
    Inventors: Chow Seng Guan, John Briar, Loreto Y. Cantillep
  • Publication number: 20020056570
    Abstract: A molded flexible circuit assembly and method of forming a molded flexible circuit assembly which use a molded stiffener, and do not require any additional type of stiffener, are described. A molded stiffener is formed on a flexible tape at the same time molded encapsulation units are formed to encapsulate circuit die which are attached to the flexible tape. The molded stiffeners provide adequate rigidity for processing of the molded flexible circuit assembly. When the stiffeners are no longer needed they are removed at the same time the mold runners are removed. No additional processing steps are required for either the formation or removal of the molded stiffeners.
    Type: Application
    Filed: January 14, 2002
    Publication date: May 16, 2002
    Applicant: ST ASSEMBLY TEST SERVICES PTE LTD
    Inventors: John Briar, Raymundo M. Camenforte