Patents by Inventor John Brothers
John Brothers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11694393Abstract: A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.Type: GrantFiled: June 18, 2021Date of Patent: July 4, 2023Inventors: Jeongjoon Yoo, Sundeep Krishnadasan, Soojung Ryu, Seokyoon Jung, John Brothers
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Publication number: 20210375030Abstract: A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.Type: ApplicationFiled: June 18, 2021Publication date: December 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jeongjoon YOO, Sundeep KRISHNADASAN, Soojung RYU, Seokyoon JUNG, John BROTHERS
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Patent number: 11074744Abstract: A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.Type: GrantFiled: April 24, 2020Date of Patent: July 27, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jeongjoon Yoo, Sundeep Krishnadasan, Soojung Ryu, Seokyoon Jung, John Brothers
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Publication number: 20200320780Abstract: A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.Type: ApplicationFiled: April 24, 2020Publication date: October 8, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jeongjoon YOO, Sundeep KRISHNADASAN, Soojung RYU, Seokyoon JUNG, John BROTHERS
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Patent number: 10672184Abstract: A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.Type: GrantFiled: May 7, 2018Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeongjoon Yoo, Sundeep Krishnadasan, Soojung Ryu, Seokyoon Jung, John Brothers
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Publication number: 20180300946Abstract: A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.Type: ApplicationFiled: May 7, 2018Publication date: October 18, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Jeongjoon YOO, Sundeep KRISHNADASAN, Soojung RYU, Seokyoon JUNG, John BROTHERS
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Patent number: 10061591Abstract: A method for reducing execution of redundant threads in a processing environment. The method includes detecting threads that include redundant work among many different threads. Multiple threads from the detected threads are grouped into one or more thread clusters based on determining same thread computation results. Execution of all but a particular one thread in each of the one or more thread clusters is suppressed. The particular one thread in each of the one or more thread clusters is executed. Results determined from execution of the particular one thread in each of the one or more thread clusters are broadcasted to other threads in each of the one or more thread clusters.Type: GrantFiled: February 26, 2015Date of Patent: August 28, 2018Assignee: Samsung Electronics Company, Ltd.Inventors: Boris Beylin, John Brothers, Santosh Abraham, Lingjie Xu, Maxim Lukyanov, Alex Grosul
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Patent number: 9984497Abstract: A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.Type: GrantFiled: August 11, 2015Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeongjoon Yoo, Sundeep Krishnadasan, Soojung Ryu, Seokyoon Jung, John Brothers
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Publication number: 20180082181Abstract: A neural network is trained to generate feature maps and associated weights. Reordering is performed to generate a functionally equivalent network. The reordering may be performed to improve at least one of compression of the weights, load balancing, and execution. In one implementation, zero value weights are grouped, permitting them to be skipped during execution.Type: ApplicationFiled: January 31, 2017Publication date: March 22, 2018Inventors: John BROTHERS, Zhengping JI, Qiang ZHENG
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Patent number: 9892534Abstract: A method of performing path rendering includes selecting a tile including a path from tiles in a frame based on tile bin data, splitting the selected tile into a plurality of first sub-tiles, selecting a first sub-tile that does not include the path from the plurality of first sub-tiles, and updating an initial winding number of the selected first sub-tile. The tile bin data includes an initial winding number of each of the tiles in the frame.Type: GrantFiled: April 7, 2016Date of Patent: February 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jeongjoon Yoo, Sundeep Krishnadasan, Jaedon Lee, John Brothers, Soojung Ryu, Wonjong Lee
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Publication number: 20170039743Abstract: A method of performing path rendering includes selecting a tile including a path from tiles in a frame based on tile bin data, splitting the selected tile into a plurality of first sub-tiles, selecting a first sub-tile that does not include the path from the plurality of first sub-tiles, and updating an initial winding number of the selected first sub-tile. The tile bin data includes an initial winding number of each of the tiles in the frame.Type: ApplicationFiled: April 7, 2016Publication date: February 9, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeongjoon YOO, Sundeep KRISHNADASAN, Jaedon LEE, John BROTHERS, Soojung RYU, Wonjong LEE
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Publication number: 20160265835Abstract: A cryogenic freezer having a housing defining an interior chamber. A first and second fan are positioned in the chamber and are spaced apart from each other. At least one motor is drivingly connected to the fans so that, upon activation of the motor, the fans circulate air through the interior chamber in the same direction.Type: ApplicationFiled: March 9, 2016Publication date: September 15, 2016Inventor: John Brothers
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Publication number: 20160042561Abstract: A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.Type: ApplicationFiled: August 11, 2015Publication date: February 11, 2016Applicant: Samsung Electronics Co., Ltd.Inventors: Jeongjoon Yoo, Sundeep Krishnadasan, Soojung Ryu, Seokyoon Jung, John Brothers
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Publication number: 20150378733Abstract: A method for reducing execution of redundant threads in a processing environment. The method includes detecting threads that include redundant work among many different threads. Multiple threads from the detected threads are grouped into one or more thread clusters based on determining same thread computation results. Execution of all but a particular one thread in each of the one or more thread clusters is suppressed. The particular one thread in each of the one or more thread clusters is executed. Results determined from execution of the particular one thread in each of the one or more thread clusters are broadcasted to other threads in each of the one or more thread clusters.Type: ApplicationFiled: February 26, 2015Publication date: December 31, 2015Inventors: Boris Beylin, John Brothers, Santosh Abraham, Lingjie Xu, Maxim Lukyanov, Alex Grosul
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Patent number: 9204159Abstract: Included are embodiments for processing video data. At least one embodiment includes a logic configured to receive video data having a format chosen from at least two formats and logic configured to receive an instruction from an instruction set including an indication of the format of the video data. Some embodiments include first parallel logic configured to process video data according to a first format in response to the indication is the first format and second parallel logic configured to process the video data according to a second format in response to the indication is the second format.Type: GrantFiled: June 15, 2007Date of Patent: December 1, 2015Assignee: VIA TECHNOLOGIES, INC.Inventors: Zahid Hussain, John Brothers, Jim Xu
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Publication number: 20150081932Abstract: According to one general aspect, an apparatus may include a source unit, a destination unit, and a plurality of interconnect wires. The source unit may be configured to store, at least temporarily, data, wherein the data is written to a storage structure in a plurality of data structures. The destination unit may be configured to receive at least a portion of the data from the source unit. The plurality of interconnect wires may be configured to transmit, the at least a portion of the data between the source unit and the destination unit. The source unit may include a transmission management unit configured to re-order the data to a re-ordered format, and wherein the re-ordered format is configured to reduce power incurred during the transmission of the at least a portion of the data across the plurality of interconnect wires.Type: ApplicationFiled: February 11, 2014Publication date: March 19, 2015Inventors: Karthik RAMANI, Santhosh PILLAI, John BROTHERS, Santosh ABRAHAM
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Patent number: 8817029Abstract: A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.Type: GrantFiled: August 30, 2006Date of Patent: August 26, 2014Assignee: Via Technologies, Inc.Inventors: John Brothers, Timour Paltashev, Hsilin Huang, Qunfeng Liao
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Patent number: 8803897Abstract: Disclosed herein is a graphics-processing unit (GPU) having an internal memory for general-purpose use and applications thereof. Such a GPU includes a first internal memory, an execution unit coupled to the first internal memory, and an interface configured to couple the first internal memory to a second internal memory of an other processing unit. The first internal memory may comprise a stacked dynamic random access memory (DRAM) or an embedded DRAM. The interface may be further configured to couple the first internal memory to a display device. The GPU may also include another interface configured to couple the first internal memory to a central processing unit. In addition, the GPU may be embodied in software and/or included in a computing system.Type: GrantFiled: November 11, 2009Date of Patent: August 12, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Greg Sadowski, Konstantine Iourcha, John Brothers
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Patent number: 8736627Abstract: Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO's are arranged in coordination with serial processing units, such as in a pipeline processing environment. The multiple FIFO's contain pointers to entry addresses in a common buffer. Each subsequent FIFO receives only pointers that correspond to data that has not been rejected by the corresponding processing unit. Rejected pointers are moved to a free list for reallocation to later data.Type: GrantFiled: December 19, 2006Date of Patent: May 27, 2014Assignee: Via Technologies, Inc.Inventor: John Brothers
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Patent number: 8681162Abstract: A programmable graphics processing unit (GPU) includes a first shader stage configured to receive slice data from a frame buffer and perform variable length decoding (VLD), wherein the first shader stage outputs data to a first buffer within the frame buffer; a second shader stage configured to receive the output data from the first shader stage and perform transformation and motion compensation on the slice data, wherein the second shader stage outputs decoded slice data to a second buffer within the frame buffer; a third shader stage configured to receive the decoded slice data and perform in-loop deblocking filtering (IDF) on the frame buffer; a fourth shader stage configured to perform post-processing on the frame buffer; and a scheduler configured to schedule execution of the shader stages, the scheduler comprising a plurality of counter registers; wherein execution of the shader stages is synchronized utilizing the counter registers.Type: GrantFiled: October 15, 2010Date of Patent: March 25, 2014Assignee: VIA Technologies, Inc.Inventors: Timour Paltashev, John Brothers, Yi-Jung Su, Yang (Jeff) Jiao