Patents by Inventor John Byron Tolle

John Byron Tolle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

REDUCED STRAIN Si/SiGe HETEROEPITAXY STACKS FOR 3D DRAM

Publication number: 20230012819

Abstract: Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.

Type: Application

Filed: July 8, 2022

Publication date: January 19, 2023

Inventors: John Byron Tolle, Tomohiko Kitajima, Thomas John Kirschenheiter, Patricia M. Liu, Zuoming Zhu, Joe Margetis, Fredrick David Fishburn, Abdul Wahab Mohammed, Gill Yong Lee

REDUCED STRAIN Si/SiGe HETEROEPITAXY STACKS FOR 3D DRAM