Abstract: A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetric agents, and at a given stage of the symmetric arbitration assert a priority agent bus request. The priority agent bus request may be shared with another priority agent. This may permit the additional agent to access the bus in a fair manner that behaves as though it were an additional symmetric agent in the system.

Abstract: A straddle adapter includes first and second plates and a side end. The side end joins the first and second plates at an edge such that the first and second plates are spaced apart and substantially parallel to each other. An edge of a printed circuit board is received between inner surfaces of the first and second plates. The outer surfaces of the first and second plates include snap connectors or other structure for mounting separate first and second edge connectors thereto. The adapter maintains the edge connectors at a predetermined separation distance. The inner surfaces of the first and second plate include deformable rails that deform as the edge of the circuit board is inserted between the first and second plates. The deformable rails compensate for variations in thickness of the circuit board and secure the adapter to the circuit board.

Abstract: A clock buffer circuit for multiple phase complementary clocking signals that receives a plurality of corresponding enabling signals and generates a like plurality of clock signals in response thereto. Each clocking signal is generated by a buffer module including a resistor, a pull-up transistor and a pull-down transistor, which are connected in series between a positive power supply and ground, with the clocking signal being taken from the node between the pull-up and pull-down transistors. In each module, before the clocking signal shifts from a low state to a high, the pull-down transistor is on so that the clocking signal is at a low state. The pull-up transistor in each module is controlled by the corresponding enabling signal and is enabled to begin conducting at the time that the clocking signal is to shift to a high state.