Patents by Inventor John C. Carney

John C. Carney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9846658
    Abstract: In one embodiment, packet memory and resource memory of a memory are independently managed, with regions of packet memory being freed of packets and temporarily made available to resource memory. In one embodiment, packet memory regions are dynamically made available to resource memory so that in-service system upgrade (ISSU) of a packet switching device can be performed without having to statically allocate (as per prior systems) twice the memory space required by resource memory during normal packet processing operations. One embodiment dynamically collects fragments of packet memory stored in packet memory to form a contiguous region of memory that can be used by resource memory in a memory system that is shared between many clients in a routing complex. One embodiment assigns a contiguous region no longer used by packet memory to resource memory, and from resource memory to packet memory, dynamically without packet loss or pause.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: December 19, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Mohammed Ismael Tatar, Promode Nedungadi, Naader Hasani, John C. Carney
  • Patent number: 9413627
    Abstract: A network device may include first logic configured to count data units passing through the network device and to produce a counter value. The network device may include second logic configured to receive the counter value when an indicator is present, and to store the counter value. The network device may include third logic configured to sample the second logic, to receive the counter value, and to operate on the counter value to produce a result.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Juniper Networks, Inc.
    Inventors: John C. Carney, Thomas Radogna
  • Patent number: 9256548
    Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Donald Edward Steiss, Marvin Wayne Martinez, Jr., John H. W. Bettink, John C. Carney, Mark Warden Hervin
  • Publication number: 20150301963
    Abstract: In one embodiment, packet memory and resource memory of a memory are independently managed, with regions of packet memory being freed of packets and temporarily made available to resource memory. In one embodiment, packet memory regions are dynamically made available to resource memory so that in-service system upgrade (ISSU) of a packet switching device can be performed without having to statically allocate (as per prior systems) twice the memory space required by resource memory during normal packet processing operations. One embodiment dynamically collects fragments of packet memory stored in packet memory to form a contiguous region of memory that can be used by resource memory in a memory system that is shared between many clients in a routing complex. One embodiment assigns a contiguous region no longer used by packet memory to resource memory, and from resource memory to packet memory, dynamically without packet loss or pause.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 22, 2015
    Applicant: Cisco Technology, Inc., a corporation of California
    Inventors: Mohammed Ismael Tatar, Promode Nedungadi, Naader Hasani, John C. Carney
  • Publication number: 20150117246
    Abstract: A network device may include first logic configured to count data units passing through the network device and to produce a counter value. The network device may include second logic configured to receive the counter value when an indicator is present, and to store the counter value. The network device may include third logic configured to sample the second logic, to receive the counter value, and to operate on the counter value to produce a result.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 30, 2015
    Inventors: John C. CARNEY, Thomas Radogna
  • Patent number: 8923124
    Abstract: A network device may include first logic configured to count data units passing through the network device and to produce a counter value. The network device may include second logic configured to receive the counter value when an indicator is present, and to store the counter value. The network device may include third logic configured to sample the second logic, to receive the counter value, and to operate on the counter value to produce a result.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: December 30, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: John C. Carney, Thomas Radogna
  • Patent number: 8774185
    Abstract: A service is applied in a packet switching device to both directions of a flow of packets through the packet switching device, with the application of this Layer-4 to layer-7 service to one direction requiring state information shared from the application of the service to packets traversing in the other direction. The service (e.g. firewall, network address translation) can be applied by different processing complexes which do not share memory; thus, state information is communicated between the processing complexes. When the service is applied by a single processing complex, packets can be directed explicitly to the single processing complex. The inline application of services in a packet switching system typically eliminates the need to change a packet's path through the packet switching system to that through a dedicated application server, and may eliminate the need for a dedicated services card or blade server.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 8, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: John C. Carney, Timothy P. Donahue, Michael E. Lipman, David Delano Ward, Doron Oz
  • Publication number: 20140149712
    Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Inventors: Donald Edward Steiss, Marvin Wayne Martinez, JR., John H. W. Bettink, John C. Carney, Mark Warden Hervin
  • Patent number: 8713575
    Abstract: A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data across the processors. Appropriate ones of the processors are configured to process the data. The reorder logic is configured to receive the data processed by the processors, reorder the data, and output the reordered data.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 29, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: John C Carney, Michael E Lipman
  • Patent number: 8531964
    Abstract: A packet scheduler may include logic configured to receive packet information. The packet scheduler may include logic to receive an operating parameter associated with a downstream device that operates with cell-based traffic. The packet scheduler may include logic perform a packet to cell transformation to produce an output based on the operating parameter. The packet scheduler may include logic to use the output to compensate for the downstream device.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: September 10, 2013
    Assignee: Juniper Networks, Inc.
    Inventor: John C. Carney
  • Patent number: 8428055
    Abstract: A system receives a set of datagrams and forms frames based on the datagrams, where at least one of the frames includes data associated with multiple ones of the datagrams. The system writes the frames to memory to form superframes in the memory, where each of the superframes includes multiple ones of frames. The system reads the superframes from the memory, recreates the datagrams based on the superframes, and outputs the datagrams.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: April 23, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: David Lipschutz, John C Carney, Thomas V Radogna
  • Patent number: 8320247
    Abstract: A method may include receiving a data unit and identifying a state of a memory storing data units. The method may include selecting a threshold value having a first threshold unit or a second threshold unit based on the state of the memory. The method may include comparing the threshold value to a queue state using the first threshold unit if the memory is in a first state. The method may include comparing the threshold value to the queue state using the second threshold unit if the memory is in a second state.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: November 27, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Paul J. Giacobbe, John C. Carney
  • Publication number: 20120266181
    Abstract: A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data across the processors. Appropriate ones of the processors are configured to process the data. The reorder logic is configured to receive the data processed by the processors, reorder the data, and output the reordered data.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: Juniper Networks, Inc.
    Inventors: John C. Carney, Michael E. Lipman
  • Patent number: 8234653
    Abstract: A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data across the processors. Appropriate ones of the processors are configured to process the data. The reorder logic is configured to receive the data processed by the processors, reorder the data, and output the reordered data.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: July 31, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: John C Carney, Michael E Lipman
  • Publication number: 20120063467
    Abstract: A packet scheduler may include logic configured to receive packet information. The packet scheduler may include logic to receive an operating parameter associated with a downstream device that operates with cell-based traffic. The packet scheduler may include logic perform a packet to cell transformation to produce an output based on the operating parameter. The packet scheduler may include logic to use the output to compensate for the downstream device.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 15, 2012
    Applicant: JUNIPER NETWORKS, INC.
    Inventor: John C. CARNEY
  • Publication number: 20120027015
    Abstract: A service is applied in a packet switching device to both directions of a flow of packets through the packet switching device, with the application of this Layer-4 to layer-7 service to one direction requiring state information shared from the application of the service to packets traversing in the other direction. The service (e.g. firewall, network address translation) can be applied by different processing complexes which do not share memory; thus, state information is communicated between the processing complexes. When the service is applied by a single processing complex, packets can be directed explicitly to the single processing complex. The inline application of services in a packet switching system typically eliminates the need to change a packet's path through the packet switching system to that through a dedicated application server, and may eliminate the need for a dedicated services card or blade server.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 2, 2012
    Applicant: Cisco Technology, Inc., a corporation of California
    Inventors: John C. Carney, Timothy P. Donahue, Michael E. Lipman, David Delano Ward, Doron Oz
  • Patent number: 8082463
    Abstract: A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert the measurement value into a control value. A delay circuit may be adjusted by the control value to alter an amount of delay of a signal.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 20, 2011
    Assignee: Juniper Networks, Inc.
    Inventor: John C. Carney
  • Patent number: 8081572
    Abstract: A packet scheduler may include logic configured to receive packet information. The packet scheduler may include logic to receive an operating parameter associated with a downstream device that operates with cell-based traffic. The packet scheduler may include logic perform a packet to cell transformation to produce an output based on the operating parameter. The packet scheduler may include logic to use the output to compensate for the downstream device.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: December 20, 2011
    Assignee: Juniper Networks, Inc.
    Inventor: John C. Carney
  • Publication number: 20110122892
    Abstract: A system receives a set of datagrams and forms frames based on the datagrams, where at least one of the frames includes data associated with multiple ones of the datagrams. The system writes the frames to memory to form superframes in the memory, where each of the superframes includes multiple ones of frames. The system reads the superframes from the memory, recreates the datagrams based on the superframes, and outputs the datagrams.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: David Lipschutz, John C. Carney, Thomas V. Radogna
  • Patent number: 7903644
    Abstract: A system receives a set of datagrams and forms frames based on the datagrams, where at least one of the frames includes data associated with multiple ones of the datagrams. The system writes the frames to memory to form superframes in the memory, where each of the superframes includes multiple ones of frames. The system reads the superframes from the memory, recreates the datagrams based on the superframes, and outputs the datagrams.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: March 8, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: David Lipschutz, John C Carney, Thomas V Radogna