Abstract: A latch (29) is set by a clock (33) to turn on power switch (FET 5). The latch (29) is reset by high voltage comparator (21), by a 50 percent clock delay (35) and by a low-voltage-to-charging-current comparator (19). The voltage at turn-on is compared with a up-ramping reference (15) until it equals an operating reference (17). A temporary delay (pulse circuit 39 and gate 37) is provided before the low voltage comparison can be effective. The delay prevents response to parasitic effects across the power switch (5). Excess drive is prevented resulting from low output currents and malfunctions, and at turn-on.