Abstract: A method of designing a reset circuit for a digital integrated circuit (IC) layout is described. The reset circuit is designed with the intention of making it visually non-detectable in the digital IC layout by implementing the reset circuit entirely in digital elements and then using standardized digital layout cells and routing such that the reset circuit is essentially non-discernible from the digital circuitry of the IC device layout. In addition, circuit elements are designed using devices having dimensions that are essentially the same as typical digital devices in the digital IC layout.

Abstract: A single-ended power supply under-voltage level detection circuit included first and second stages of devices stacks coupled between a power supply signal and a reference potential. As the power supply increases it overcomes device threshold voltages in the first stage causing it to enable the second stage. As the power supply signal continues to increase and reaches a second voltage level, the second stage outputs a level indicator signal which indicates that the power supply is greater than or equal to a predetermined voltage level. A power-down signal can be externally applied to devices in the first and second stages so as to disable the detection circuit no matter what the power supply signal level is. In addition, the detection circuit can be used in a power-on-reset (POR) circuit to detect when the power supply has reached a predetermined voltage level so as to cause the POR circuit to output a POR signal an extended time interval afterwards.

Abstract: A differential true single phase latch and flip-flop designed to embody logic functions is described. The logic function embodied latch includes a first circuit branch including first input switching devices for receiving a first set of input signals which include input signals and their corresponding complements and for outputting a first output signal having a logic state representative of the results of a logic function performed on said first set of input signals and a second circuit branch including second input switching devices for receiving the complement of the at least two input signals and can include the at least two input signals and for outputting a non-inverted output signal. First and second input switching devices are configured so as to cause the latch to perform logic functions on the input signals and latch output states corresponding to the results logic functions on its non-inverted and inverted outputs in the same clock phase.

Abstract: A power-on-reset (POR) circuit having a reduced sized charging capacitor is described which includes a voltage detection portion, a delay portion, and a POR signal generation portion. The voltage level detection portion functions to provide a level indicator signal after the power supply has reached a predetermined voltage level. The delay portion in response to the level indicator signal indicating that the power supply is greater than or equal to the predetermined voltage level charges a chargeable node to an inverter trip point voltage level in a predetermined delay time interval dependent on a capacitive element and a diode connected MOS device both connected to the chargeable node. The POR signal generation portion, in response to the voltage trip point level on the chargeable node, outputs a POR signal an extended time interval afterwards.

Abstract: The present invention relates to a system and method for programming VROM links. The system has an address selection circuit connected to the VROM link for selecting an address in the VROM link in which to program. A polarity control circuit is also connected to the VROM link. The polarity control circuit allows one to control the directional flow of a current used in programming the VROM link.