Abstract: As frequency spectra are produced continuously at a speed that is too fast for realtime display, they are accumulated in a memory. After a block of these frequency spectra have been accumulated, they are read back from the memory and displayed on a display device that permits the display of multiple frequency spectra along a time axis. Markers allow delta-time measurements to be made between different spectra in the display. Continuous storage into a circular memory can be stopped and the display of the accumulated frequency spectra started by the detection of the occurrence of a pre-defined spectra event.

Abstract: A voltage comparator for an analog to digital converter is provided which includes several differential amplifier stages connected in cascade that determine the existence of a voltage difference between the two input signals and amplify this voltage difference successively. The comparator further includes offset correction voltage circuits which are connected to each differential amplifier stage and allow for the correction of errors caused by the mismatching of the devices internal to each of the differntial amplifier stages.

Abstract: A sampling switch circuit is provided for an analog to digital converter that provides for the scaling of two switches connected to the converter comparator. The comparator receives two input voltages which are switched to reference voltages. To correct any offset voltage resulting from a mismatch between the switch circuitry, this invention provides for one switch to be attached to a capacitor while the second switch is attached to the capacitive array that digitizes the analog input. These two switches are proportionally fabricated according to the size of their respective capacitive load in order to reduce any voltage difference resulting from the capacitive coupling internal to the switches. The switching circuitry also implements a sequence of switching to correct the offset error from capacitive coupling.

Abstract: An analog to digital converter is provided which includes a binary weighted capacitor array connected with a series of resistors structured as an array. The converter provides for charge correction to compensate for any capacitance deviation in the capacitor array. The converter includes a charge redistribution sequence under the control of a microcomputer to determine the digital value of the analog input using the resistor array to determine the least significant bit positions of the analog input. This same resistor array is also used to correct for capacitor value deviations in the binary weighted capacitor array.

Abstract: Error correction circuitry for an analog to digital converter is disclosed which provides for the correction of charge in a charge redistribution converter architecture. This conversion technique as implemented requires that a binary weighted capacitor array be present where the capacitors are accurately binarily weighted in decreasing value. The charge correction circuitry allows for the correction of any deviations of binary weighted capacitance value by adding or subtracting charge from the capacitor array. This is accomplished by the use of a resistor array connected to a capacitor that is equal in capacitance to the smallest capacitor in the capacitor array. The converter includes a microcomputer which determines the charge error for each of the individual capacitors together with the total charge error for the capacitive array coupling with the comparitor.

Abstract: A voltage comparator circuit suitable for a semiconductor integrated circuit device comprised of a variable impedance being controlled by input voltages that are to be compared with one another and a feedback circuit comprised of a pair of cross-coupled transistors each having a gain of unity to provide a differential signal of infinite gain to a single ended output circuit.