Patents by Inventor John C. Federkins

John C. Federkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5959982
    Abstract: A Time Division Duplex (TDD) wireless system utilizes an identical TDD IC engine in both base station and remote stations. In the base station the clock input to the TDD IC is halted once in the middle of each time slice to provide a central guard band between transmit and receive portions that determines the maximum range of the system. At the remote stations clock halts are programmed and utilized to provide guard bands to position transmit and receive portions in each time slice to accommodate propagation delay based on separation of a remote station from the base station. In a preferred embodiment the remote stations determine range to the base and a controller programs clock halts based on the range finding. In one aspect a TDD IC engine is used with a minimum fixed central guard band and a time slice of a first duration at a first clock frequency. Clock frequency is increased and the clock halted to provide increased range at the same time slice duration.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: September 28, 1999
    Assignee: Adicom Wireless, Inc.
    Inventors: John C Federkins, Namvar Kiaie, Ronald Ross, Karl K Yick
  • Patent number: 5123014
    Abstract: A method and apparatus for arranging an HDLC data link to transport a special class of data such as, for example, synchronization or other signalling informaiton, in addition to the normal data transported by the data link is provided. According to the invention, at the sending end of the link the all-1's sequence corresponding to the idle sequence between individual HDLC packets is detected. Once eight (8) consecutive 1's are detected, a desired number of 1's is removed and a like number of synchronization bits are inserted in their place. At the receiving end of the link the inserted synchronization bits are detected, removed, and a like number of 1's inserted in their place.
    Type: Grant
    Filed: February 27, 1990
    Date of Patent: June 16, 1992
    Assignee: Motorola, Inc.
    Inventors: John C. Federkins, Charles L. Whittington, Hueiming Yang