Patents by Inventor John C. Flake
John C. Flake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230287579Abstract: This application relates to new process that utilizes electrodes that incorporate acids that facilitate upgrading of methane and other low molecular weight alkanes to higher order hydrocarbon molecules, such as paraffins, olefins, and aromatics, at temperatures less than 250° C. A primary focus of the invention includes methane conversion to ethylene. The first step of the process includes acid containing electrodes that facilitate the activation of the alkane in the anode layer of the electrochemical reactor. Subsequent steps include the separation of protons from produced longer chain hydrocarbons followed by subsequent electrochemical reduction of the protons to yield hydrogen at the cathode or protons combined with oxygen at the cathode to yield water. The reaction steps in the anode upgrade methane to higher order hydrocarbon products.Type: ApplicationFiled: February 9, 2023Publication date: September 14, 2023Inventors: Christopher George Arges, John C. Flake, Yuxin Fang
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Patent number: 11591699Abstract: This application relates to new process that utilizes electrodes that incorporate acids that facilitate upgrading of methane and other low molecular weight alkanes to higher order hydrocarbon molecules, such as paraffins, olefins, and aromatics, at temperatures less than 250° C. A primary focus of the invention includes methane conversion to ethylene. The first step of the process includes acid containing electrodes that facilitate the activation of the alkane in the anode layer of the electrochemical reactor. Subsequent steps include the separation of protons from produced longer chain hydrocarbons followed by subsequent electrochemical reduction of the protons to yield hydrogen at the cathode or protons combined with oxygen at the cathode to yield water. The reaction steps in the anode upgrade methane to higher order hydrocarbon products.Type: GrantFiled: April 12, 2019Date of Patent: February 28, 2023Assignee: Board of Supervisors of Louisiana State UniversityInventors: Christopher George Arges, John C. Flake, Yuxin Fang
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Publication number: 20210164115Abstract: This application relates to new process that utilizes electrodes that incorporate acids that facilitate upgrading of methane and other low molecular weight alkanes to higher order hydrocarbon molecules, such as paraffins, olefins, and aromatics, at temperatures less than 250° C. A primary focus of the invention includes methane conversion to ethylene. The first step of the process includes acid containing electrodes that facilitate the activation of the alkane in the anode layer of the electrochemical reactor. Subsequent steps include the separation of protons from produced longer chain hydrocarbons followed by subsequent electrochemical reduction of the protons to yield hydrogen at the cathode or protons combined with oxygen at the cathode to yield water. The reaction steps in the anode upgrade methane to higher order hydrocarbon products.Type: ApplicationFiled: April 12, 2019Publication date: June 3, 2021Inventors: Christopher George Arges, John C. Flake, Yuxin Fang
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Publication number: 20120171560Abstract: The present invention provides composite anodes comprising particles composed of silicon and lithium silicate, active and inactive anode materials, and binders, for lithium rechargeable batteries, wherein the particles composed of silicon and lithium silicate are prepared via treating silicon particles with lithium hydroxide in a wet process. Cycle life and characteristics and capacity of a secondary battery adopting the composite anode can be greatly improved.Type: ApplicationFiled: February 1, 2012Publication date: July 5, 2012Applicant: ELECTROCHEMICAL MATERIALS, LLCInventors: WANLI XU, JOHN C. FLAKE
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Publication number: 20120164528Abstract: A composite anode for lithium secondary battery which has an active anode material layer formed on a conductive substrate and an interfacial film coated on the active anode material layer, wherein the active anode material layer includes carbonaceous materials, other active and inactive materials, and a binder. The anode increases degree of the anode active material utilization and the cycle life and characteristic and capacity of the battery can be improved.Type: ApplicationFiled: February 1, 2012Publication date: June 28, 2012Applicant: ELECTROCHEMICAL MATERIALS, LLCInventors: WANLI XU, JOHN C. FLAKE
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Publication number: 20120121977Abstract: An anode active material comprising silicon particles with an interfacial layer formed on the surface of the silicon is provided. The interfacial layer has good electron conductivity, elasticity and adhesion among anode materials, thereby enhancing anode capacity and reducing stress caused by expansion of silicon particles during charge and discharge cycles. Direct contact between silicon particles and electrolyte is remarkably reduced as well. In addition, anodes and lithium batteries including the anode active material exhibit excellent capacity and cycle efficiency.Type: ApplicationFiled: December 27, 2011Publication date: May 17, 2012Applicant: Electrochemical Materials, LLCInventors: WANLI XU, JOHN C. FLAKE
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Patent number: 7989347Abstract: A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ?200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator.Type: GrantFiled: March 30, 2006Date of Patent: August 2, 2011Assignee: Freescale Semiconductor, Inc.Inventor: John C. Flake
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Patent number: 7579279Abstract: A method for processing semiconductor wafers is disclosed. A solution is applied to a semiconductor wafer to prevent dendrites and electrolytic reactions at the surface of metal interconnects. The solution can be applied during a CMP process or during a post CMP cleaning process. The solution may include a surfactant and a corrosion inhibitor. In one embodiment, the concentration of the surfactant in the solution is less than approximately one percent by weight and the concentration of the corrosion inhibitor in the solution is less than approximately one percent by weight. The solution may also include a solvent and a cosolvent. In an alternate embodiment, the solution includes a solvent and a cosolvent without the surfactant and corrosion inhibitor. In one embodiment, the CMP process and post CMP cleaning process can be performed in the presence of light having a wavelength of less than approximately one micron.Type: GrantFiled: February 1, 2007Date of Patent: August 25, 2009Assignee: Freescale Semiconductor, Inc.Inventors: John C. Flake, Kevin E. Cooper, Saifi Usmani
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Publication number: 20090170306Abstract: A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ?200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator.Type: ApplicationFiled: March 30, 2006Publication date: July 2, 2009Applicant: FREESCALE SEMICONDUTOR INCInventor: John C Flake
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Patent number: 7456105Abstract: This disclosure describes a low particle concentration formulation for slurry which is particularly useful in continuous CMP polishing of copper layers during semiconductor wafer manufacture. The slurry is characterized by particle concentrations generally less than 2 wt %, and advantageously less than 1 wt %. In particular embodiments, where the particle concentration is in a range of 50 to 450 PPM, an 8-fold increase in polishing rate over reactive liquid slurries has been realized. Slurries thus formulated also achieve a reduction in defectivity and in the variations in planarity from wafer to wafer during manufacture, by improving the stability of polishing quality. The slurry formulations permit substantial cost savings over traditional 2-component, reactive liquid and fixed/bonded abrasive slurries. In addition the formulations provides an advantageous way during CMP to easily change the selectivity or rate of removal of one film material vs. another.Type: GrantFiled: December 17, 2002Date of Patent: November 25, 2008Assignees: AMD, Inc., Motorola, Inc.Inventors: Kevin Elliot Cooper, Jennifer Lynn Cooper, Janos Farkas, John C. Flake, Johannes Friedrich Groschopf, Yuri Solomentsev
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Patent number: 7387970Abstract: A method for processing semiconductor wafers is disclosed. A semiconductor wafer is provided to a semiconductor processing stage where a block copolymer surfactant (BCS) is applied to the wafer surface. In one embodiment, the BCS includes a hydrophobic portion and a hydrophilic portion. Alternatively, the BCS may be a silicone-containing BCS. In one embodiment, the BCS is within an aqueous solution where the concentration of the BCS within the aqueous solution is less than one percent by weight. Also disclosed is an aqueous solution including abrasive particles and a BCS having a hydrophobic portion and a hydrophilic portion. The abrasive particles may include silica, alumina, or ceria.Type: GrantFiled: May 7, 2003Date of Patent: June 17, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Kevin E. Cooper, John C. Flake, Johannes Groschopf, Yuri E. Solomentsev
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Patent number: 7188630Abstract: A method for processing semiconductor wafers is disclosed. A solution is applied to a semiconductor wafer to prevent dendrites and electrolytic reactions at the surface of metal interconnects. The solution can be applied during a CMP process or during a post CMP cleaning process. The solution may include a surfactant and a corrosion inhibitor. In one embodiment, the concentration of the surfactant in the solution is less than approximately one percent by weight and the concentration of the corrosion inhibitor in the solution is less than approximately one percent by weight. The solution may also include a solvent and a cosolvent. In an alternate embodiment, the solution includes a solvent and a cosolvent without the surfactant and corrosion inhibitor. In one embodiment, the CMP process and post CMP cleaning process can be performed in the presence of light having a wavelength of less than approximately one micron.Type: GrantFiled: May 7, 2003Date of Patent: March 13, 2007Assignee: Freescale Semiconductor, Inc.Inventors: John C. Flake, Kevin E. Cooper, Saifi Usmani
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Patent number: 6838354Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.Type: GrantFiled: December 20, 2002Date of Patent: January 4, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
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Publication number: 20040266173Abstract: A method for forming an electrically conductive layer having predetermined patterns for semiconductor devices includes providing a substrate, forming an insulation layer having OH functional groups on the substrate, forming a patterned polymer layer on the insulation layer, etching the insulation layer to create a patterned insulation layer which has the same patterns as the patterned polymer layer, stripping the patterned polymer layer to expose the patterned insulation layer, treating the patterned insulation layer with a coupling agent which reacts with the OH functional groups, treating the patterned insulation layer with a catalyst-containing solution in which the catalyst reacts with the coupling agent, and depositing electrically conductive material on the patterned insulation layer which is catalytically active.Type: ApplicationFiled: June 2, 2004Publication date: December 30, 2004Applicant: International Business Machines CorporationInventors: Paul S. Andry, John C. Flake, Bruno Michel, Takatoshi Tsujimura
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Publication number: 20040224426Abstract: A method for processing semiconductor wafers is disclosed. A semiconductor wafer is provided to a semiconductor processing stage where a block copolymer surfactant (BCS) is applied to the wafer surface. In one embodiment, the BCS includes a hydrophobic portion and a hydrophilic portion. Alternatively, the BCS may be a silicone-containing BCS. In one embodiment, the BCS is within an aqueous solution where the concentration of the BCS within the aqueous solution is less than one percent by weight. Also disclosed is an aqueous solution including abrasive particles and a BCS having a hydrophobic portion and a hydrophilic portion. The abrasive particles may include silica, alumina, or ceria.Type: ApplicationFiled: May 7, 2003Publication date: November 11, 2004Inventors: Kevin E. Cooper, John C. Flake, Johannes Groschopf, Yuri E. Solomentsev
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Publication number: 20040224521Abstract: A method for processing semiconductor wafers is disclosed. A solution is applied to a semiconductor wafer to prevent dendrites and electrolytic reactions at the surface of metal interconnects. The solution can be applied during a CMP process or during a post CMP cleaning process. The solution may include a surfactant and a corrosion inhibitor. In one embodiment, the concentration of the surfactant in the solution is less than approximately one percent by weight and the concentration of the corrosion inhibitor in the solution is less than approximately one percent by weight. The solution may also include a solvent and a cosolvent. In an alternate embodiment, the solution includes a solvent and a cosolvent without the surfactant and corrosion inhibitor. In one embodiment, the CMP process and post CMP cleaning process can be performed in the presence of light having a wavelength of less than approximately one micron.Type: ApplicationFiled: May 7, 2003Publication date: November 11, 2004Inventors: John C. Flake, Kevin E. Cooper, Saifi Usmani
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Patent number: 6767828Abstract: A method for forming an electrically conductive layer having predetermined patterns for semiconductor devices includes providing a substrate, forming an insulation layer having OH functional groups on the substrate, forming a patterned polymer layer on the insulation layer, etching the insulation layer to create a patterned insulation layer which has the same patterns as the patterned polymer layer, stripping the patterned polymer layer to expose the patterned insulation layer, treating the patterned insulation layer with a coupling agent which reacts with the OH functional groups, treating the patterned insulation layer with a catalyst-containing solution in which the catalyst reacts with the coupling agent, and depositing electrically conductive material on the patterned insulation layer which is catalytically active.Type: GrantFiled: October 5, 2001Date of Patent: July 27, 2004Assignee: International Business Machines CorporationInventors: Paul S. Andry, John C. Flake, Bruno Michel, Takatoshi Tsujimura
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Publication number: 20040119134Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
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Patent number: 6620719Abstract: A method for forming ohmic contacts for semiconductor devices, in accordance with the present invention, includes forming a layer containing metal which includes dopants integrally formed therein. The layer containing metal is patterned to form components for a semiconductor device, and a semiconductor layer is deposited for contacting the layer containing metal. The semiconductor device is annealed to outdiffuse dopants from the layer containing metal into the semiconductor layer to form ohmic contacts therebetween.Type: GrantFiled: March 31, 2000Date of Patent: September 16, 2003Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Evan George Colgan, John C. Flake, Peter Fryer, William Graham, Eugene O'Sullivan
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Publication number: 20030068480Abstract: A method for forming an electrically conductive layer having predetermined patterns for semiconductor devices includes providing a substrate, forming an insulation layer having OH functional groups on the substrate, forming a patterned polymer layer on the insulation layer, etching the insulation layer to create a patterned insulation layer which has the same patterns as the patterned polymer layer, stripping the patterned polymer layer to expose the patterned insulation layer, treating the patterned insulation layer with a coupling agent which reacts with the OH functional groups, treating the patterned insulation layer with a catalyst-containing solution in which the catalyst reacts with the coupling agent, and depositing electrically conductive material on the patterned insulation layer which is catalytically active.Type: ApplicationFiled: October 5, 2001Publication date: April 10, 2003Applicant: International Business Machines CorporationInventors: Paul S. Andry, John C. Flake, Bruno Michel, Takatoshi Tsujimura