Patents by Inventor John C. Foster
John C. Foster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240139507Abstract: Flexible catheters adapted to be inserted into a body to deliver high-voltage, fast (e.g., microsecond, sub-microsecond, nanosecond, picosecond, etc.) electrical energy to target tissue may include a plurality of conductive layers, that may be coaxial. These catheters and method of using them to treat tissue are configured to reduce or avoid arcing.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: David J. DANITZ, Kevin L. MOSS, Wesley C. JOE, Christopher J. FOSTER, Gary L. BOSECK, Xitlalic Y. SOTO-SIDA, Robert MASTON, John P. LUNSFORD
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Patent number: 11931570Abstract: Flexible catheters adapted to be inserted into a body to deliver high-voltage, fast (e.g., microsecond, sub-microsecond, nanosecond, picosecond, etc.) electrical energy to target tissue may include a plurality of conductive layers, that may be coaxial. These catheters and method of using them to treat tissue are configured to reduce or avoid arcing.Type: GrantFiled: January 3, 2023Date of Patent: March 19, 2024Assignee: Pulse Biosciences, Inc.Inventors: David J. Danitz, Kevin L. Moss, Wesley C. Joe, Christopher J. Foster, Gary L. Boseck, Xitlalic Y. Soto-Sida, Robert Maston, John P. Lunsford
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Patent number: 11930267Abstract: An electronic device may be provided with control circuitry, wireless transceiver circuitry, and a display. The electronic device may be used to provide information to a user in response to being pointed at a particular object. The control circuitry may determine when the electronic device is pointed at a particular object using wireless control circuitry and/or motion sensor circuitry. In response to determining that the electronic device is pointed at a particular object, the control circuitry may take suitable action. This may include, for example, displaying information about an object when the electronic device is pointed at the object, displaying control icons for electronic equipment when the electronic device is pointed at the electronic equipment, and/or displaying a virtual object when the electronic device is pointed at real world object.Type: GrantFiled: June 18, 2021Date of Patent: March 12, 2024Assignee: Apple Inc.Inventors: Adam S. Meyer, Peter C. Tsoi, Duncan Robert Kerr, Martha Evans Hankey, John B. Morrell, James H. Foster
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Publication number: 20230100579Abstract: A nanopore cell may include a well having a seamless porous electrode and hydrophobic sidewalls. The seamless porous electrode may be formed by depositing porous electrode material on a planar electrode support layer formed by a conductive layer island and a dielectric layer. The porous electrode material may form uniform seamless columns and may be protected during manufacturing by depositing a selectably removable protective layer thereon. The well may be formed by forming and then patterning hydrophobic cladding over the protective layer. The protective layer may be removed to expose the seamless porous electrode at the bottom of the well.Type: ApplicationFiled: November 23, 2022Publication date: March 30, 2023Inventors: John C. FOSTER, Kenneth A. HONER, Marowen NG
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Publication number: 20130332268Abstract: Methods for selling items over a computer network can include: after a first set of customers has purchased, during a first time period, at least a threshold value or number of items of a first set of items: (a) during a second time period after the first period, offering for sale to the first set of customers an index set of items; (b) throughout the second period, preventing substantially all persons other than the first set of customers from purchasing the index set of items; and (c) during a third time period, offering for sale to a second set of customers, different from the first set of customers, any of the index set of items not sold to the first set of customers during the second period.Type: ApplicationFiled: June 4, 2013Publication date: December 12, 2013Inventor: John C. Foster
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Patent number: 7498222Abstract: A high K layer, such as aluminum oxide or hafnium oxide, may be formed with a deposition process that uses an ion implantation to damage portions of the high K material that are to be later etched. More particularly, in one implementation, a semiconductor device is manufactured by forming a first dielectric over a substrate, forming a charge storage element over the first dielectric, forming a second dielectric above the charge storage element, implantation ions into select portions of the second dielectric, and etching the ion implanted select portions of the second dielectric.Type: GrantFiled: March 9, 2006Date of Patent: March 3, 2009Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: John C. Foster, Scott Bell, Allison Holbrook, Simon S. Chan, Phillip Jones
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Patent number: 6602781Abstract: A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.Type: GrantFiled: December 12, 2000Date of Patent: August 5, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Paul R. Besser, Matthew Buynoski, John C. Foster, Paul L. King, Eric N. Paton
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Patent number: 6562718Abstract: A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.Type: GrantFiled: December 6, 2000Date of Patent: May 13, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Ercan Adem, Jacques J. Bertrand, Paul R. Besser, Matthew S. Buynoski, John C. Foster, Paul L. King, George J. Kluth, Minh V. Ngo, Eric N. Paton, Christy Mei-Chu Woo
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Patent number: 6475874Abstract: A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.Type: GrantFiled: December 7, 2000Date of Patent: November 5, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Paul R. Besser, Matthew S. Buynoski, John C. Foster, Paul L. King, Eric N. Paton
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Patent number: 6465309Abstract: A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.Type: GrantFiled: December 12, 2000Date of Patent: October 15, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Paul R. Besser, Matthew Buynoski, John C. Foster, Paul L. King, Eric N. Paton
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Publication number: 20020111021Abstract: Nickel salicide processing is implemented by forming a non-stoicheiometric mediating layer, such as ozonated SiOx, to control the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions. Embodiments of the present invention comprise forming silicon nitride sidewall spacers on the side surfaces of the gate electrode.Type: ApplicationFiled: February 13, 2001Publication date: August 15, 2002Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Eric N. Paton, Terri J. Kitson, Jeffrey S. Glick, John C. Foster
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Publication number: 20020102848Abstract: A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.Type: ApplicationFiled: December 7, 2000Publication date: August 1, 2002Applicant: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Paul R. Besser, Matthew . Buynoski, John C. Foster, Paul L. King, Eric N. Paton
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Patent number: 6387804Abstract: Shorting between a transistor gate electrode and associated source/drain regions due to metal silicide formation on the sidewall spacers is prevented by passivating the sidewall spacer surfaces with a mixture of ozone and water. Embodiments of the invention include spraying the wafer with or immersing the wafer in, a saturated solution of ozone in water.Type: GrantFiled: September 19, 2000Date of Patent: May 14, 2002Assignee: Advanced Micro Devices, Inc.Inventor: John C. Foster
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Patent number: 6372644Abstract: Bridging between nickel silicide layers on a gate electrode and associated source/drain regions along silicon nitride sidewall spacers is prevented by hydrogen passivation of the exposed surfaces of the silicon nitride sidewall spacers. Embodiments include treating the silicon nitride sidewall spacers with a solution of HF and H2O, at a HF:H2O volume ratio of about 100:1 to about 200:1 for up to about 60 seconds at room temperature. Hydrogen passivation reduces the number of silicon dangling bonds, thereby avoiding reaction with subsequently deposited nickel and, hence, avoiding the formation of a bridging film of nickel silicide on the sidewall spacers.Type: GrantFiled: February 22, 2001Date of Patent: April 16, 2002Assignee: Advanced Micro Devices, Inc.Inventors: John C. Foster, Paul L. King
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Patent number: 6368963Abstract: Shorting between a transistor gate electrode and associated source/drain regions due to metal silicide formation on the sidewall spacers is prevented by passivating the sidewall spacer surfaces with a solution of iodine and ethanol. Embodiments of the invention include spraying the wafer with or immersing the wafer in, a solution of iodine in ethanol.Type: GrantFiled: September 12, 2000Date of Patent: April 9, 2002Assignee: Advanced Micro Devices, Inc.Inventor: John C. Foster
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Patent number: 6368950Abstract: A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.Type: GrantFiled: December 12, 2000Date of Patent: April 9, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Paul R. Besser, Matthew S. Buynoski, John C. Foster, Paul L. King, Eric N. Paton
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Patent number: 6342414Abstract: A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.Type: GrantFiled: December 12, 2000Date of Patent: January 29, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Paul R. Besser, Matthew S. Buynoski, John C. Foster, Paul L. King, Eric N. Paton
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Patent number: 4938535Abstract: An adjustable shoulder/lap seat belt adapter in the form of an elongated strap, has fixably mounted on one face thereof a central strip of one of a hook-and-loop type fastener material tape intermediate the ends of the elongated strap. Short length strips of the other of hook-and-loop type fastener tape are affixed to opposite ends of the elongated strap on the same face. Closed loops are formed at the end of the elongated strap about a shoulder strap and a lap strap of a shoulder/lap seat belt securing an occupant to an automotive motor vehicle seat, preventing ride up of the shoulder strap on the torso of the seat occupant, misuse of the shoulder strap, and eliminating the need for constant repetitive readjusting of the shoulder strap position. A swivel-mounted snap clamp affixed to the one face of the adapter elongated strap, clamps to the edge of the shoulder strap with a swivel axis oriented approximately 65.degree. to the center line of the elongated strap.Type: GrantFiled: June 14, 1989Date of Patent: July 3, 1990Inventors: Dolores Condon, Theresa A. Foster, John C. Foster
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Patent number: 4155136Abstract: Intensity of vibrations emitted by tool and workpiece acted upon is reduced by an enveloping mat of floppy fibres. In a heel attacher, for instance, the mat reduces by 14 or more decibels, and an operator incurs no risk of injury to his hands should they be in the path of the mat when it is moved to or from a heel and shoe being attached.Type: GrantFiled: April 20, 1978Date of Patent: May 22, 1979Assignee: USM CorporationInventor: John C. Foster